Abstract: A spine testing device having bearing supports located at a horizontal distance from one another in order to support opposite ends of an arrow, a measuring unit for determining a spine value of the arrow and a display unit for displaying the spine value. The bearing supports are equipped with a weighing device in order to measure a force emanating from the arrow. A stop is located in an area between the weighing devices at such a height that the arrow can be brought by a specified distance from a horizontal starting position into a bending position by exerting a force at a point of application of the same located between the ends of the arrow, in which bending position the application portion of the arrow lies in contact with the stop. The measuring unit includes an evaluation device having means for establishing a bending force acting on the arrow.

Abstract: A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode.

Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.

Abstract: Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations.

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.

Abstract: Systems, methods, and articles to provide customized control of a cooking appliance. A user provides a selection of one or more ending characteristics for a food product. A processor-based device determines one or more output food preparation parameters based on the user's selection of the one or more ending characteristics. Measurements of temperature, power, or other characteristics may be obtained during cooking process. A cooking program controlling the cooking process may be revised or updated based at least in part on the obtained measurements or analysis of the measurements. Estimations or projections about the cooking process may be presented to a user via a user interface of the cooking appliance or a user interface of a computing device (e.g., smartphone) associated with the user. The processor-based device may autonomously detect a temperature scale of a temperature setting input by a user without requiring the user to specify the temperature scale.

Abstract: Apparatuses, methods and storage media associated with single-ended sensing array design are disclosed herein. In embodiments, a memory device may include bitcell arrays, clipper circuitry, read merge circuitry, and a set dominant latch (SDL). The clipper circuitry may be coupled to a read port node of a first bitcell array of the bitcell arrays and a local bitline (LBL) node, the clipper circuitry to provide a voltage drop between the read port node and the LBL node. The read merge circuitry coupled to the clipper circuitry at the LBL node, the read merge circuitry to drive a value of a global bitline (GBL) node based on a value of the LBL node. The SDL coupled to the GBL node to sense the value of the GBL node. Other embodiments may be described and/or claimed.

Abstract: A viscosity coefficient calculation device includes a resistivity acquiring part that acquires, for each plurality of periods of time until a specific strains is generated when a load is applied to a sample, a value of deformation resistivity corresponding to an apparent modulus of elasticity when modulus of elasticity considered to be in accordance with Hook's law, and an output part that outputs a value of a viscosity coefficient of the sample from the value of the deformation resistivity for the each plurality of periods of time acquired by the resistivity acquiring part using a relational expression associating the deformation resistivity with the viscosity coefficient, the relational expression being a fractional function for periods of time, the relational expression analytically obtained by substituting the deformation resistivity into a first order differential equation for a stress and a strain obtained from a configuration expression of a viscoelasticity model.

Abstract: The present disclosure provides storage elements, such as storage transistors, wherein at least one storage mechanism is provided on the basis of a ferroelectric material formed in the buried insulating layer of an SOI transistor architecture. In further illustrative embodiments, one further storage mechanism is implemented in the gate electrode structure, thereby providing increased overall information density. In some illustrative embodiments, the storage mechanism in the gate electrode structure is provided in the form of a ferroelectric material.

Abstract: Control of a plurality of electronically commutated motors is effected using a control unit and a power unit. The power unit enables the provision of commutation signals to each controlled motor. The control unit comprises a DSP and a FPGA. An input memory of the FPGA is mapped to the DSP. In use, the DSP determines motor repositioning signals, on the basis of a received motor position demand signal describing demanded motor positions and the encoded motor position data, and loads the motor repositioning signals into the input memory of the FPGA. The FPGA is operable to generate motor driving current signals for driving the motors into the demanded motor positions, on the basis of the motor repositioning signals and motor phase current samples collected by the power unit, and to output the motor driving current signals to the power unit.

Abstract: A method of non-destructive testing includes locating an ultrasonic transducer with respect to a component having a visually-inaccessible structure to collect B-scan data from at least one B-scan of the component and to collect C-scan data from at least one C-scan of the component. The method also includes filtering the B-scan data and the C-scan data to remove random noise and coherent noise based on predetermined geometric information about the visually-inaccessible structure to obtain filtered data. The method further includes performing linear signal processing and nonlinear signal processing to determine a damage index for a plurality of voxels representing the visually-inaccessible structure from the filtered B-scan data and the filtered C-scan data to generate a V-scan image. A method of non-destructive testing of a wind turbine blade and an ultrasound system are also disclosed.

Abstract: An integrated circuit structure includes a first fuse line formed in a first metal layer; a second fuse line formed in the first metal layer; a first pair of fuse wings formed in the first metal layer on opposite sides of a first end of the first fuse line; a second pair of fuse wings formed in the first metal layer on opposites sides of a first end of the second fuse line; a third pair of fuse wings formed in the first metal layer on opposite sides of a second end of the first fuse line; and a fourth pair of fuse wings formed in the first metal layer on opposites sides of a second end of the second fuse line. The first and second pairs of fuse wings share a first common fuse wing and the third and fourth pairs of wings share a second common fuse wing.

Abstract: Apparatus including an array of memory cells and a controller configured to apply a particular programming pulse to a plurality of memory cells having a first subset of memory cells having respective desired data states that are lower than a particular data state and a second subset of memory cells having respective desired data states that are higher than or equal to the particular data state, to at least partially inhibit each memory cell of the first subset of memory cells from programming while not inhibiting any memory cell of the second subset of memory cells from programming and while applying the particular programming pulse, then to apply a subsequent programming pulse while not inhibiting any memory cell of the first subset of memory cells from programming other than any memory cell of the first subset of memory cells having its respective desired data state equal to a lowest data state, and while not inhibiting any memory cell of the second subset of memory cells from programming.

Abstract: A tablet for use with a consumer appliance is provided. The tablet may be removably attachable to the consumer appliance, which may charge the tablet through an integrated USB charger. The tablet may be in wired or wireless communication with the appliance and/or a remote server. In this manner, the tablet may provide the user with timely information related to operation of the consumer appliance or directly from the internet.