Abstract: A semiconductor device may include a plurality of memory banks and an output buffer that couples to the plurality of memory banks. The output buffer may produce a data voltage signal representative of data to be read from at least one of the plurality of memory banks. The semiconductor device may also include a driver circuit having a pulse generator and a pull-down switch that couples the output buffer to ground, such that the pull-down switch provides the data voltage signal to the output buffer. The semiconductor device may also include a test mode circuit that determines whether the data voltage signal is acceptable and sends an enable signal to the pulse generator in response to the data voltage signal not being acceptable. The enable signal causes the pulse generator to effectively operate with variations in processing, temperature, and voltage properties associated with testing.

Abstract: The present disclosure includes apparatuses and methods related to selectable trim settings on a memory device. An example apparatus can store a number of sets of trim settings and select a particular set of trims settings of the number of sets of trim settings based on desired operational characteristics for the array of memory cells.

Abstract: Disclosed is an inch pounds per turn (IPPT) computing device that provides for the calculation of IPPT of a garage door spring coil. The IPPT computing device computes the IPPT required of the garage door spring coil by measuring the strain induced on a calibrated shaft used to lift the weight of the garage door. The IPPT computing device is inserted into the winding end cone of a garage door torsion spring assembly, and the door is slightly lifted off of the floor. This measurement is done by disabling the cable ends spring end so the counterbalance force is removed from the door. The IPPT tool measures the torque (strain on the calibrated rod) needed to lift the door and inputs the torque value automatically into an IPPT calculator mounted on the tool. When other door parameters are entered into the calculator, the IPPT is calculated.

Abstract: According to one embodiment, a memory system classifies a plurality of nonvolatile memory dies connected to a plurality of channels, into a plurality of die groups such that each of the plurality of nonvolatile memory dies belongs to only one die group. The memory system performs a data write/read operation for one die group of the plurality of die groups in accordance with an I/O command from a host designating one of a plurality of regions including at least one region corresponding to each die group. The memory system manages a group of free blocks in the nonvolatile memory for each of the plurality of die group by using a plurality of free block pools corresponding to the plurality of die groups.

Abstract: Systems and methods for determining kerogen porosity of a formation for downhole operations are described herein. An example method may include obtaining core pyrolysis data from a wellbore disposed in a formation. A thermal characteristic of the formation proximate to the wellbore, such as a time-temperature burial history of the formation, may also be determined. A kerogen porosity of the formation may be calculated based, at least in part, on the pyrolysis data and the thermal characteristic, and a downhole operation may be performed based, at least in part, on the calculated kerogen porosity.

Abstract: A memory device comprises a plurality of stacks of word lines, the word lines in the stacks having first vertical sides and second vertical sides opposite the first vertical sides, and a first plurality of strings and a second plurality of strings disposed respectively on the first vertical sides and the second vertical sides of the word lines in a particular stack in the plurality of stacks. The second plurality of strings is offset from the first plurality of strings in a direction along which the word lines in the particular stack extend. A first program operation includes applying a shielding voltage to a first string in the first plurality of strings and a fourth string in the second plurality of strings, and applying a program voltage to a second string in the second plurality of strings and a third string in the first plurality of strings.

Abstract: Data is stored in a multi-level MRAM (MLC MRAM) cell in a manner that reduces transition states that require high energy. A new data block is received, and the new data block is divided into one or more sub-groups of bits, with each sub-group comprising at least two bits. Each sub-group is assigned data bit locations in a memory store. The received bits are compared with sub-groups present at the data bit locations to determine subgroups of hot bits. For each subgroup of hot bits, an encoding flag value is determined by XORing their most significant bits. The most significant bits of each subgroup of hot bits are complemented and the encoding flag is SET. A data block is generated to establish a data group for each subgroup of hot bits including the subgroup of hot bits and the encoding flag for that subgroup.

Abstract: Devices are described that include a multi-layered structure that is non-magnetic at room temperature, and which comprises alternating layers of Co and at least one other element E (that is preferably Al; or Al alloyed with Ga, Ge, Sn or combinations thereof). The composition of this structure is represented by Co1-xEx, with x being in the range from 0.45 to 0.55. The structure is in contact with a first magnetic layer that includes a Heusler compound. An MRAM element may be formed by overlying, in turn, the first magnetic layer with a tunnel barrier, and the tunnel barrier with a second magnetic layer (whose magnetic moment is switchable). Improved performance of the MRAM element may be obtained by placing an optional pinning layer between the first magnetic layer and the tunnel barrier.

Abstract: A memory device having a plurality sections of memory cells, such as ferroelectric memory cells may provide for concurrent access to memory cells within independent sections of the memory device. A first memory cell may be activated, and it may be determined that a second memory cell is independent of the first memory cell. If the second memory cell is independent of the first memory cell, the second memory cell may be activated prior to the conclusion of operations at the first memory cell. Latching hardware at memory sections may latch addresses at the memory sections in order to allow a new address to be provided to a different section to access the second memory cell.

Abstract: Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition.

Abstract: A semiconductor memory device and a data reading method capable of appropriately reading data stored in memory cells are provided. The semiconductor memory device includes: a memory cell array including multiple memory cells and having a known-data storage area storing determination data used for determining appropriateness or inappropriateness of a value of each of a reading voltage applied to a memory cell when reading data stored in the memory cell and a comparative current used for a comparison with a current flowing through a memory cell according to stored data; a decoder that applies the reading voltage to a memory cell to be read according to an address representing the memory cell to be read; and a sense amplifier including a comparison circuit that outputs a comparison result acquired by comparing a current flowing through the memory cell to be read 66 according to stored data with the comparative current.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for performing read mode tuning. An apparatus includes an error rate storage circuit that determines error rate information. An apparatus includes a mode selection circuit that determines a read mode of a plurality of read modes for reading a set of memory cells based on error rate information. The plurality of read modes may include a fast read mode and a normal read mode. An apparatus includes a read circuit that performs a read on a set of memory cells based on a read mode.

Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, first and second magnetic layers, a first nonmagnetic layer and a controller. The conductive layer includes first and second portions, and a third portion positioned between the first and second portions. The conductive layer includes a first metal. The first magnetic layer is separated from the third portion. The second magnetic layer is provided between the third portion and the first magnetic layer. The first nonmagnetic layer is provided between the first and second magnetic layers. The controller is electrically connected to the first and second portions. The second magnetic layer has first and second lattice lengths. The first lattice length is longer than the second lattice length. The controller implements a first operation of supplying a first current to the conductive layer, and a second operation of supplying a second current to the conductive layer.

Abstract: A memory device having a plurality sections of memory cells, such as ferroelectric memory cells (hybrid RAM (HRAM) cells) may provide for concurrent access to memory cells within independent sections of the memory device. A first memory cell may be activated, and it may be determined that a second memory cell is independent of the first memory cell. If the second memory cell is independent of the first memory cell, the second memory cell may be activated prior to the conclusion of operations at the first memory cell. Latching hardware at memory sections may latch addresses at the memory sections in order to allow a new address to be provided to a different section to access the second memory cell.

Abstract: A memory device includes a memory array including a plurality of memory cells; and an array timer coupled to the memory array, configured to generate an output timing signal based on a V-I stable input and an analog reference signal, wherein: the V-I stable input is from a bandgap supply circuit, the analog reference signal is from an analog reference block, and the output timing signal is configured to control the memory array.

Abstract: A semiconductor device includes an N number of sub-blocks each of including a memory cell array, a setting register specifying number of entry data for pre-searching, of first to N-th entry data divided and correspond respectively to the sub-blocks, and a search data changing unit changing a data arrangement order for search data input based on a value of the register. A sub-block for pre-searching searches for entry data matching with data for pre-searching in accordance with the arrangement order changed by the changing unit, in response to an instruction, and outputs a search result representing matching or non-matching. A sub-block for post-searching searches for entry data matching with data for post-searching other than the data for pre-searching, of entry data stored in association with each row of the array, based on a search result of the sub-block for pre-searching, and outputs a search result representing matching or non-matching.

Abstract: Antiferromagnetic magneto-electric spin-orbit read (AFSOR) logic devices are presented. The devices include a voltage-controlled magnetoelectric (ME) layer that switches polarization in response to an electric field from the applied voltage and a narrow channel conductor of a spin-orbit coupling (SOC) material on the ME layer. One or more sources and one or more drains, each optionally formed of ferromagnetic material, are provided on the SOC material.

Abstract: Apparatus including a memory array further include an analog voltage generation circuit, an analog controller, a data cache, a data cache controller, and a master controller. The master controller is configured to generate an indication in response to an interpreted command. The analog controller is configured to determine, in response to the indication, what analog voltages should be generated by the analog voltage generation circuit for the apparatus to perform the interpreted command. The data cache controller is configured to determine, in response to the indication, whether the data cache should be configured to accept data from the memory array or to provide data to the memory array for the apparatus to perform the interpreted command.

Abstract: Methods and systems for internal timing schemes are provided. A data strobe (DQS) signal is received at a memory device. The DQS signal is shifted in a negative direction relative to a clock of the memory device to cause a fail point of a flip flop of the memory device. After causing the fail point, the DQS signal is shifted in a positive direction relative to the clock. A transition edge of an internal write signal (IWS) is centered in a DQS period, such as a write preamble. The IWS indicates that a write command is to be captured. Moreover, centering the transition edge includes selectively delaying the IWS in the negative direction.

Abstract: A method and a system for determining bit values in a non-volatile memory having a number of cells each for storing a bit value are disclosed. The method includes the steps of: a) providing a first test sensing voltage to the cells and calculating a cell count; b) providing another test sensing voltage to the cells and calculating a difference of the cell counts between this step and previous step; c) providing still another test sensing voltage and calculating another difference of the cell counts between this step and previous step; d) processing step c) for N times; e) calculating differential amounts of cell counts and assigning an index number to each group of cells; f) choosing a voltage as an updated sensing voltage.