Abstract: In various embodiments, a method of encoding a custom cooking program includes receiving at least one sensor reading associated with food, determining at least one characteristic of the food based on the at least one sensor reading, generating cooking instructions for the food based on the at least one characteristic, and storing data that associates the cooking instructions with the food.

Abstract: A buffer circuit may include: a current mirror circuit suitable for selectively forming a first current mirror corresponding to a first power source voltage, and a second current mirror corresponding to a second power source voltage; and a differential pair coupled to the current mirror circuit, and suitable for forming a current path with the first current mirror or the second current mirror, amplifying a differential signal corresponding to a difference between a reference voltage and input data received through an input terminal, and outputting the amplified differential signal to an output terminal as a buffer output signal.

Abstract: A circuit for adjusting a select gate voltage of a non-volatile memory is provided. The circuit includes a well, a select gate, and an adjustment unit. There is a capacitive coupling between the well and the select gate. The adjustment unit generates a driving voltage for the select gate based on a non-constant voltage.

Abstract: The disclosure is related a method for testing and measuring the performances of electrical components on a semiconductor IC device through a test apparatus (also referred to as a testline) disposed in a scribe line between the semiconductor IC devices on a wafer. The test apparatus may include a built-in self-test (BIST) circuit and a duplication of the electrical components subjected to the performance measurement. Minimum and maximum testing voltages are provided to the test apparatus, where the range of voltage between the minimum and maximum testing voltages are divided into a plurality of testing operational voltages which are applied to the test apparatus. For each testing operational voltages, a memory array operation test is performed, where at least one of the testing operational voltages resulting in a performance failure is identified as the minimal operating voltage of the memory array.

Abstract: Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. The comparator includes a sense current buffer configured to buffer the sense current and the comparator is further configured to provide an output signal having a logic level indicative of a result of the comparison.

Abstract: In the present invention: a power consumption calculation unit sets target speeds in a plurality of sections of a track; the power consumption calculation unit calculates, on the basis of the target speeds, the power consumption when the track is traveled; a target speed change unit changes combinations of target speeds in the plurality of sections set by the power consumption calculation unit; an evaluation value calculation unit calculates an evaluation value on the basis of an evaluation function for each combination of target speeds; the evaluation function is a function in which the power consumption calculated by the power consumption calculation unit is multiplied by a prescribed weight; and a target speed determination unit sets the combination of target speeds in which the evaluation value is smallest as the target speed of the vehicle in each section.

Abstract: Apparatuses and methods for calibrating sense amplifiers in a semiconductor memory are disclosed. An example apparatus includes an amplifier circuit and a calibration circuit. The amplifier circuit is configured to be coupled to a supply voltage and a reference voltage, and when activated the amplifier circuit is configured to provide an output signal at an output that is complementary to an input signal provided to an input. When activated by a calibration signal, the calibration circuit is configured to provide a calibration voltage to the output of the amplifier circuit, wherein the calibration voltage is an equilibration voltage between the supply voltage and the reference voltage provided to the amplifier circuit.

Abstract: The present disclosure includes apparatuses and methods related to shifting data. A number of embodiments of the present disclosure include an apparatus comprising a shift register comprising an initial stage and a final stage. The shift register may be configured such that a clock signal may be initiated at the final stage of the shift register.

Abstract: Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state, after the first applying, determining that the memory cell failed to place in the desired state, after the determining, second applying a second signal to the memory cell, wherein the second signal corresponds to another state which is different than the desired state, and after the second applying, third applying a third signal to the memory cell to program the memory cell to the desired state, wherein the third signal corresponds to the desired state. Additional method and apparatus are described.

Abstract: One embodiment of the invention includes moving target indication (MTI) system. The system includes an MTI data processor configured to receive time-sampled location indicators associated with an approximate location of a moving target in a geographic scene of interest and to generate a moving target indicator associated with the moving target based on the time-sampled location indicators. The system also includes an image integrator configured to receive the moving target indicator associated with the moving target, to receive geography data associated with the geographic scene of interest, and to integrate the moving target indicator into the geography data as a three-dimensional moving target indicator at an approximate geographic location of the moving target.

Abstract: A system and method for determining a condition of a filter filtering fuel associated with an engine. Input information relating to the operation of the engine is provided by a plurality of sensors. At least some of the input information is used to determine a plurality of input variables, the plurality of input variables representing a plurality of engine operating conditions including engine run time, engine torque and engine speed. An algorithm incorporating the input variables is used to determine the condition of the filter. Information concerning the condition of the filter may be output to a user such as an operator or service provider.

Abstract: A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels. In some examples, the controller may be configured to define, from the memory array, a plurality of die-sets based on respective chip enable lines associated with the plurality of dies, wherein each die-set of the plurality of die-sets includes at least one die from each of the plurality of channels; define, from a selected die-set of the plurality of die-sets, a plurality of blocksets, wherein each blockset includes a block from each die of the selected die-set; receive a unit of data to be stored; and issue commands that cause the unit of data to be stored in blocks of a selected blockset of the plurality of blocksets.

Abstract: In general, embodiments of the technology relate to improving read performance of solid-state storage by using decoding schemes deemed particularly suitable for the read operation that is currently being performed. More specifically, embodiments of the technology relate to using program/erase (P/E) cycle values, retention times, and page numbers in order to determine the appropriate decoding parameters to use when reading data that has been previously stored in the solid-state storage.

Abstract: Systems and methods are described for compacting operating parameter sets in a data storage device. Data storage device may be configured to maintain multiple operating parameter sets, each of which stores various parameters for interacting with different memory elements within the device. The data storage device may further be limited in the total number of operating parameter sets that can be maintained in the device at any given time. Thus, the data storage device may be required at various times to combine two or more operating parameter sets, to enable creation of a new operating parameter set. Because each operating parameter set can contain a number of parameters, identification of similar sets for combination can be computationally intensive. To identify similar sets in an efficient manner, a device as disclosed herein is enabled to reduce a dimensionality of each set, and locate similar sets under that reduced dimensionality.

Abstract: A system for detecting faults in building equipment includes an integration fault detector, a kernel density fault detector, and a fault detector selector. The integration fault detector is configured to detect faults in the building equipment by analyzing time series data using an integration fault detection technique. The kernel density fault detector is configured to detect faults in the building equipment by analyzing the time series data using a kernel density estimation fault detection technique. The fault detector selector is configured to select the integration fault detector or the kernel density fault detector for use in detecting faults in the building equipment based on an attribute of the time series data.

Abstract: A memory system performs verification when writing to memory. It is possible that the memory system may be missing some components (or components may be otherwise unavailable). To account for missing or unavailable components when performing verification, the memory system uses a pattern of data that includes a mask identifying the missing or unavailable components. The mask is used to force a predetermined result of the verification for the missing or unavailable portions of the memory structure so that results of the verification that correspond to the missing or unavailable components are not counted as errors.

Abstract: Techniques for reducing a downshift in the threshold voltage of a select gate transistor of a memory device. Due to an electric field in a NAND string, holes can move in a charge-trapping layer from a dummy memory cell to a select gate transistor and combine with electrons in the transistor, reducing the threshold voltage. In one approach, the electric field is reduced at the end of a sensing operation by ramping down the voltage of the dummy memory cells before ramping down the voltage of the select gate transistors. The ramp down of the voltage of the selected memory cells can occur after ramping down the voltage of the dummy memory cells and before ramping down of the voltage of the select gate transistors. A further option involves elevating the voltage of the select gate transistors before it is ramped down.

Abstract: A nonvolatile memory device includes a first cell string including a first dummy cell and connected to a selected string select line, a second cell string including a second dummy cell and connected to the selected string select line, a page buffer circuit configured to select one of the first and second cell strings to read data in a read operation, and a control logic circuit configured to apply a first bit line voltage to a bit line connected to the selected one of the first and second cell strings and a second bit line voltage to a bit line connected to an unselected one of the first and second cell strings in the read operation. The control logic circuit turns off the second dummy cell when the first cell string is selected and turns off the first dummy cell when the second cell string is selected.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a ROM, an SRAM, a memory and a selector. The ROM stores initialization data. At least part of the initialization data is writable to the SRAM. The memory stores information indicating whether data is written to the SRAM. The selector outputs one of data supplied from the SRAM and data supplied from the ROM in accordance with the information stored in the memory.

Abstract: Once a delay locked loop has been locked to a clock signal, an omitted clock cycle is injected into the input of the delay locked loop without stopping the operation of the delay locked loop. The omitted cycle is later detected at an output of the delay locked loop, and the delay between the input and output is determined based on the time the omitted cycle requires to propagate through the delay locked loop. Once determined, the number of cycles of delay for the delay locked loop can be used in conjunction with an internal clock signal to launch data and/or data strobes from memory devices and memory controllers such that the proper phase alignment and clock cycle alignment is achieved.