Patents Examined by Tom Thomas
  • Patent number: 10354974
    Abstract: A chip package structure and a method for forming a chip package are provided. The chip package structure includes a first package which includes at least a semiconductor die, a dielectric structure surrounding the semiconductor die, and a plurality of conductive structures penetrating through the dielectric structure and surrounding the semiconductor die. The package structure also includes an interposer substrate over the first package and a plurality of conductive features in or over the interposer substrate. The package structure further includes a second package over the interposer substrate, and the first package electrically couples the second package through the conductive structures and the conductive features.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: July 16, 2019
    Assignee: MediaTek Inc.
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Andrew C. Chang, Tao Cheng
  • Patent number: 10304995
    Abstract: A flexible electric device includes a first electrode on a flexible member, at least one semiconductor element on the first electrode, at least one filling region adjacent to the semiconductor element and a second electrode on the semiconductor element.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: May 28, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-hee Choi, Yun-seong Lee
  • Patent number: 10304938
    Abstract: Various methods and semiconductor structures for fabricating an FET device having Nickel atoms implanted in a silicide metal film on a source-drain contact region of the FET device thereby reducing resistance of the source-drain contact region of the FET device. An example fabrication method includes maskless blanket implantation of Nickel atoms across a semiconductor wafer. Nickel atoms can be implanted into silicide metal film of a source-drain contact region of nFET devices, pFET devices, or both, on a semiconductor wafer. Nickel atoms can be implanted into silicide metal film on a source-drain contact region of nFET devices and pFET devices. The silicide metal film on the source-drain contact region of the nFET device being a different material than the silicide metal film on the source-drain contact region of the pFET device.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Hemanth Jagannathan, Christian Lavoie
  • Patent number: 10297596
    Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: May 21, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Deepak Sharma, Hyun-jong Lee, Raheel Azmat, Chul-hong Park, Sang-jun Park
  • Patent number: 10290688
    Abstract: The present invention provides an AMOLED device and a manufacturing method thereof. The manufacturing method of the AMOLED device according to the present invention adopts an ink jet printing operation to form an anode of the AMOLED device and thus, compared to the prior art operations, saves one mask and reduces one round of photoengraving thereby simplifying the manufacturing operation of the AMOLED device and lowering the manufacturing costs. The AMOLED device according to the present invention comprises an anode that is formed through an ink jet printing operation, so that the manufacturing operation is simplified and the manufacturing cost is reduced.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: May 14, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Baixiang Han, Yuanchun Wu
  • Patent number: 10283518
    Abstract: A semiconductor device includes a first stacked structure having first conductive layers and first insulating layers formed alternately with each other, first semiconductor patterns passing through the first stacked structure, a coupling pattern coupled to the first semiconductor patterns, and a slit passing through the first stacked structure and the coupling pattern.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: May 7, 2019
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Seung Jun Lee
  • Patent number: 10269768
    Abstract: A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ying Ho, Jeng-Shyan Lin, Wen-I Hsu, Feng-Chi Hung, Dun-Nian Yaung, Ying-Ling Tsai
  • Patent number: 10269686
    Abstract: Embodiments of the present invention relate to a semiconductor package that includes a locking feature. The locking feature is provided by an unnatural surface roughness of a first molding compound to increase adhesion with a second molding compound. Surfaces of first molding compound are roughened by an abrasion process such that the surfaces are rougher than a natural surface roughness. The roughened surfaces of the first molding compound provide better adhesion of the second molding compound to the roughened surfaces than to untreated surfaces (e.g., surfaces with the natural surface roughness).
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: April 23, 2019
    Assignee: UTAC Headquarters PTE, LTD.
    Inventors: Suebphong Yenrudee, Saravuth Sirinorakul
  • Patent number: 10263042
    Abstract: An organic photoelectric device includes a first electrode and a second electrode facing each other, and an active layer between the first electrode and the second electrode, wherein the active layer includes an n-type semiconductor compound that is transparent in a visible ray region and represented by Chemical Formula 1, and a p-type semiconductor compound having a maximum absorption wavelength in a wavelength region of about 500 nm to about 600 nm of a visible ray region.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: April 16, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Rie Sakurai, Hiromasa Shibuya, Tadao Yagi, Kwang Hee Lee, Takkyun Ro, Sung Young Yun, Gae Hwang Lee, Dong-Seok Leem, Seon-Jeong Lim, Xavier Bulliard, Yong Wan Jin, Yeong Suk Choi, Hye Sung Choi
  • Patent number: 10262905
    Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Qing Liu, Nicolas Loubet, Scott Luning
  • Patent number: 10256347
    Abstract: The semiconductor device includes an oxide semiconductor layer including a plurality of channel formation regions arranged in the channel width direction and parallel to each other and a gate electrode layer covering a side surface and a top surface of each channel formation region with a gate insulating layer placed between the gate electrode layer and the channel formation regions. With this structure, an electric field is applied to each channel formation region from the side surface direction and the top surface direction. This makes it possible to favorably control the threshold voltage of the transistor and improve the S value thereof. Moreover, with the plurality of channel formation regions, the transistor can have increased effective channel width; thus, a decrease in on-state current can be prevented.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: April 9, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10249586
    Abstract: Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Arvin, Christopher D. Muzzy
  • Patent number: 10242953
    Abstract: Embodiments of the present invention relate to a semiconductor package with a metal-plated shield. Surfaces of molding compound are roughened by an abrasion process such that the surfaces have an unnatural surface roughness that is rougher than a natural surface roughness. The roughened surfaces provide better adhesion of the metal-plated shield to the roughened surfaces than to untreated surfaces (e.g., surfaces with the natural surface roughness). A catalyst material can be deposited on the roughened surfaces of the molding compound before a metal layer is coated on the roughened surfaces of the molding compound to speed up the time for the metal layer to adhere to the roughened surfaces of the molding compound. The metal-plated shield can include plurality of metal layers plated on top of each other.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: March 26, 2019
    Assignee: Utac Headquarters PTE. Ltd
    Inventors: Suebphong Yenrudee, Chanapat Kongpoung, Sant Hongsongkiat, Siriwanna Ounkaew, Chatchawan Injan, Saravuth Sirinorakul
  • Patent number: 10243005
    Abstract: An object is to improve reliability of a semiconductor device. A semiconductor device including a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate is provided. The driver circuit portion and the display portion include thin film transistors in which a semiconductor layer includes an oxide semiconductor; a first wiring; and a second wiring. The thin film transistors each include a source electrode layer and a drain electrode layer which each have a shape whose end portions are located on an inner side than end portions of the semiconductor layer. In the thin film transistor in the driver circuit portion, the semiconductor layer is provided between a gate electrode layer and a conductive layer. The first wiring and the second wiring are electrically connected in an opening provided in a gate insulating layer through an oxide conductive layer.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: March 26, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Masayuki Sakakura, Yoshiaki Oikawa, Kenichi Okazaki, Hotaka Maruyama
  • Patent number: 10234556
    Abstract: In a wind profiler, the number of acquisition ranges is expanded up to heights where noise is introduced into a received signal, even in the case where noise due to transmit/receive switching is introduced. A signal processing device in a wind profiler emits an electromagnetic wave pulse into a space, switches from transmitting to receiving, receives an electromagnetic wave reflected from a target to be observed, and measures wind speed from a Doppler frequency of the received electromagnetic wave, and includes an unnecessary data determiner that detects a noise section in which switching noise occurs due to the switching between transmitting and receiving, and an unnecessary data eraser that converts a received signal in the noise section to substantially insignificant data.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: March 19, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tomoya Matsuda, Taiji Harada, Takao Yamamoto
  • Patent number: 10236456
    Abstract: A compound that includes a ligand L, having the formula, is provided. In the structure of Formula I, each R1, R2, R3, R4, R4, R5, R6, R7, and R8 is independently selected from a variety of substituents; any adjacent substituents are optionally joined or fused into a ring; at least one of R3, R4, and R5 is not hydrogen; “a” is an integer from 0 to 10; (i) when a is 0, at least one of R7, R8, and an R2 adjacent to ring B, is not hydrogen, and (ii) when a is 1 to 10, at least one of an R2 adjacent to ring A and an R6 adjacent to ring C is not hydrogen; ligand L is coordinated to a metal M having an atomic weight greater than 40; and ligand L is optionally linked with other ligands to comprise a tridentate, tetradentate, pentadentate or hexadentate ligand.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: March 19, 2019
    Assignee: UNIVERSAL DISPLAY CORPORATION
    Inventors: Jui-Yi Tsai, Lichang Zeng, Alexey Borisovich Dyatkin, Walter Yeager, Edward Barron, Bin Ma, Chuanjun Xia
  • Patent number: 10217760
    Abstract: In an embodiment, the semiconductor device may include interlayer insulating layers, conductive patterns, a channel layer, cell blocking insulating layers, dummy blocking insulating layers, and a data storage layer. The interlayer insulating layers and conductive patterns may be alternately stacked. The channel layer may pass through the interlayer insulating layers and the conductive patterns. The cell blocking insulating layers may be respectively arranged between the channel layer and the conductive patterns. The dummy blocking insulating layers may be respectively arranged between the channel layer and the interlayer insulating layers, and may protrude further toward a side wall of the channel layer than the cell blocking insulating layers. The data storage layer may surround the side wall of the channel layer, and may be formed on a concavo-convex structure defined by the cell blocking insulating layers and the dummy blocking insulating layers.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: February 26, 2019
    Assignee: SK hynix Inc.
    Inventor: Wan Sup Shin
  • Patent number: 10217951
    Abstract: Conjugated polymer-based organic field-effect transistors have garnered attention since the solution processability of the semiconductor material raises the possibility of lower device fabrication costs, and considerable progress has been made on achieving high mobility systems. Further improvements in charge carrier mobility while using non-specialized deposition techniques and minimizing the volume of semiconductor used in the fabrication process are important considerations for practical implementation. Here, a method of fabricating devices is disclosed that uses a technique (for example, a scalable blade-coating technique) to cast polymer thin film devices from blend solutions with one component being the polymer semiconductor and the other being a commodity polymer. Even when mixing the semiconducting polymer with 90% polystyrene by weight, an average mobility of 2.7±0.4 cm2 V?1 s?1 can be obtained.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: February 26, 2019
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Michael J. Ford, Guillermo C. Bazan
  • Patent number: 10217803
    Abstract: An organic light-emitting diode display includes a substrate including an active area and a dead area surrounding the active area. The organic light-emitting diode display further includes a first organic light-emitting device disposed in the active area. The organic light-emitting diode display additionally includes a second organic light-emitting device disposed in the dead area, and a sensor configured to sense light emitted from the second organic light-emitting device. The first organic light-emitting device emits light in a first direction, and the second organic light-emitting device emits light in a second direction that is opposite to the first direction and is toward the sensor.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: February 26, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Sangjoon Ryu
  • Patent number: 10211421
    Abstract: A flexible film structure, a method of manufacturing the flexible film structure, and a flexible display device, the flexible film structure including a base film; and at least one functional hard coating layer on the base film, wherein the functional hard coating layer includes a siloxane polymer having an epoxy group.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: February 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-min Lee, Nam-il Koo