Patents Examined by Tom Thomas
  • Patent number: 10141507
    Abstract: The present invention relates to metal oxide based memory devices and methods for manufacturing such devices, and more particularly to memory devices having data storage materials based on metal oxide compounds fabricated with a biased plasma oxidation process which improves the interface between the memory element and a top electrode for a more a uniform electrical field during operation, which improves device reliability.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: November 27, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Yu Lin, Feng-Min Lee
  • Patent number: 10134802
    Abstract: An emissive Solid State Imager (SSI) comprised of a spatial array of digitally addressable multicolor micro pixels. Each pixel is a micro optical cavity comprising multiple photonic layers of blue-violet semiconductor light emitting diode. One of the photonic layers is used to generate light at the blue primary of the SSI. Two of the photonic layers are used to generate violet-blue excitation light which is converted with associated nanophosphors layer into the green and the red primaries of the SSI. The light generated is emitted perpendicular to the plane of the imager device via a plurality of vertical optical waveguides that extract and collimate the light generated. Each pixel diode is individually addressable to enable the pixel to simultaneously emit any combination of the colors associated with its multicolor nanophosphors converted semiconductor light emitting diode at any required on/off duty cycle for each color.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: November 20, 2018
    Assignee: Ostendo Technologies, Inc.
    Inventor: Hussein S. El-Ghoroury
  • Patent number: 10134738
    Abstract: There is provided a low power memory device with JFET device structures. Specifically, a low power memory device is provided that includes a plurality memory cells having a memory element and a JFET access device electrically coupled to the memory element. The memory cells may be isolated using diffusion based isolation.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: November 20, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Patent number: 10103142
    Abstract: Integrated circuit devices are provided. The devices may include first and second fin-shaped channel regions protruding from a substrate, and the first and second fin-shaped channel regions may define a recess therebetween. The devices may also include an isolation layer in a lower portion of the recess. The isolation layer may include a first stress liner extending along a side of the first fin-shaped channel region, a second stress liner extending along a side of the second fin-shaped channel region and an insulation liner between the first stress liner and the side of the first fin-shaped channel region and between the second stress liner and the side of the second fin-shaped channel region. The devices may further include a gate insulation layer on surfaces of upper portions of the first and second fin-shaped channel regions and a gate electrode layer on the gate insulation layer.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: October 16, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sug-hyun Sung, Jung-gun You, Gi-gwan Park
  • Patent number: 10103227
    Abstract: A method for manufacturing a power semiconductor device includes: forming a drift region of a first conductivity type, a second emitter region of a second conductivity type, a pn-junction between the second emitter region and drift region, and a first emitter region having a first doping region of the first conductivity type and a second doping region of the first conductivity type; forming a first emitter metallization in contact with the first emitter region to form an ohmic contact between the first emitter metallization and the first doping region, and to form a non-ohmic contact between the first emitter metallization and the second doping region; and forming a second emitter metallization in contact with the second emitter region. The first emitter region is formed using a mask that is aligned with respect to the second emitter region, so that the first and second doping regions are formed in aligned relation.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: October 16, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Holger Huesken, Anton Mauder, Hans-Joachim Schulze, Wolfgang Roesner
  • Patent number: 10094801
    Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity. An amplification factor of the BioFET device may be provided by a difference in capacitances associated with the gate structure on the first surface and with the interface layer formed on the second surface.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: October 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, LTD.
    Inventors: Yi-Shao Liu, Rashid Bashir, Fei-Lung Lai, Chun-wen Cheng
  • Patent number: 10095075
    Abstract: A display panel includes a display area configured to display an image, and a peripheral area adjacent to the display area. The peripheral area includes a pad area in which a plurality of output pads are disposed. The output pads are arranged in a matrix formed having M row*N column (M and N are normal numbers, M is 3 or larger than 3). Each of the output pads has a center of the output pad spaced apart from a center of an adjacent output pad by a distance D in a first direction. Each of the output pads is spaced apart from an adjacent output pad by a gap. Each of the output pads has a center of the output pad spaced apart from a center of an adjacent output pad by a pitch P in a second direction which is substantially perpendicular to the first direction. An equation “P<D/(M?1)” is satisfied.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: October 9, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sang-Moon Moh, Luck-Hyun Kim
  • Patent number: 10096624
    Abstract: Display substrates and display devices with reduced electrical resistance are disclosed. One inventive aspect includes a switching device, a first wiring and a second wiring. The switching device includes a first semiconductor layer, first and second gate insulation layers, a source electrode and a drain electrode. The source and drain electrodes are formed to electrically connect, through the first and second gate insulation layers, to the first semiconductor layer. The second wiring is formed on the second gate insulation layer and electrically connected to the first wiring.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: October 9, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ji-Yong Park, Tae-Gon Kim
  • Patent number: 10096615
    Abstract: A semiconductor device includes a cell structure; n first pad structures formed on one side of the cell structure and each configured to have a step form in which 2n layers form one stage; and n second pad structures formed on the other side of the cell structure each configured to have a step form in which 2n layers form one stage, wherein n is a natural number of 1 or higher, and the first pad structures and the second pad structures have asymmetrical step forms having different heights.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: October 9, 2018
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Sung Ik Moon
  • Patent number: 10096659
    Abstract: The present disclosure includes a top emission type organic light emitting diode display device. The top emission type organic light emitting diode display device of the disclosed present disclosure includes an overcoating layer disposed on a substrate and including a plurality of convex portions or a plurality of concave portions in which a full width at half maximum is greater than a radius, a first electrode disposed on the overcoating layer, an organic light emitting layer disposed on the first electrode, and a second electrode disposed on the organic light emitting layer.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: October 9, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Sookang Kim, Soyoung Jo, Wonhoe Koo, Jihyang Jang, Hyunsoo Lim, Mingeun Choi
  • Patent number: 10096531
    Abstract: A semiconductor device includes semiconductor body region and a surface region, the semiconductor body region including a first conductivity type first semiconductor region type and a second conductivity type second semiconductor region.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: October 9, 2018
    Assignee: Infineon Technologies AG
    Inventors: Christian Jaeger, Johannes Georg Laven, Frank Dieter Pfirsch, Alexander Philippou
  • Patent number: 10096577
    Abstract: A semiconductor memory package includes a base layer that communicates with a memory controller; at least one memory layer that is stacked on the base layer; and at least one through silicon via that penetrates through the at least one memory layer, wherein at least one signal bump for exchanging a signal with the memory controller is disposed in a first area of the base layer located to be adjacent to the memory controller, and wherein the first area corresponds to an edge area of the base layer, and a power bump for receiving power from outside of the semiconductor memory package for performing a signal processing operation on the signal is disposed in a second area of the base layer contacting the at least one through silicon via, wherein the second area corresponds to an area other than edge areas of the base layer.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: October 9, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok Kim, Chi-sung Oh
  • Patent number: 10090322
    Abstract: A method of manufacturing a semiconductor device, includes: loading a substrate including a laminated film including an insulating film and a sacrificial film, a channel hole formed in the laminated film, a charge trapping film formed on a surface in the channel hole, a first channel film formed on a surface of the charge trapping film, and a common source line exposed on the bottom of the channel hole; receiving information on a distribution of hole diameter of the channel hole; and forming a second channel film on a surface of the first channel film by supplying a first processing gas and a second processing gas to a center side and an outer peripheral side of the substrate, respectively, so as to correct the distribution of the hole diameter based on the information.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: October 2, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Satoshi Shimamoto, Toshiyuki Kikuchi, Atsushi Moriya, Masanori Nakayama, Takashi Nakagawa
  • Patent number: 10084389
    Abstract: A power module includes a substrate, a first sub-module and a second sub-module. Each of the first sub-module and the second sub-module includes a semiconductor switch and a diode. The first sub-module is formed as the high-voltage-side switching element. The second sub-module is formed as the low-voltage-side switching element. The plural electrodes of the high-voltage-side switching element and the plural electrodes of the low-voltage-side switching element are electrically connected with the conducting terminals of the corresponding semiconductor switches and the corresponding diodes. The high-voltage-side switching element is disposed on the substrate and electrically connected with the corresponding conducting parts of the substrate. The low-voltage-side switching element is disposed on the high-voltage-side switching element and electrically connected with the corresponding conducting parts of the substrate through the high-voltage-side switching element.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: September 25, 2018
    Assignee: DELTA ELECTRONICS INT'L (SINGAPORE) PTE LTD
    Inventors: Yiu-Wai Lai, Da-Jung Chen
  • Patent number: 10084071
    Abstract: A representative fin field effect transistor (FinFET) includes a substrate having a major surface; a fin structure protruding from the major surface having a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material. A bottom portion of the upper portion comprises a dopant with a first peak concentration. A middle portion is disposed between the lower portion and upper portion, where the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant. An isolation structure surrounds the fin structure, where a portion of the isolation structure adjacent to the bottom portion of the upper portion comprises the dopant with a second peak concentration equal to or greater than the first peak concentration.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen, Chao-Hsiung Wang, Chi-Wen Liu
  • Patent number: 10084085
    Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a stop layer formed over a substrate and a fin structure formed over the stop layer. The FinFET device structure includes a gate structure formed over the fin structure and a source/drain (S/D) structure adjacent to the gate structure. A bottom surface of the S/D structure is located at a position that is higher than or level with a bottom surface of the stop layer.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10085308
    Abstract: The invention provides a drawer type cooking device, wherein the mounting positions of roller-shaped shock absorbing members 10b and 10b attached to a drawer body 2 are either aligned with portions of the side walls 3b and 3b of the heating chamber 3 where fixing angles 8 of the slide rails 7 are attached and thus having enhanced rigidity, or arranged close to a bottom wall 3c of the heating chamber 3, so that when a biased operation force is applied to the door, the generation of a gap between a front side panel of the cooking device body 1 and the inner side of the door is suppressed, and the occurrence of a microwave leakage through the gap caused by not stopping the generation of microwave until the operation of a latch is thereby prevented in advance.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: September 25, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Tatsuhiko Nakamura
  • Patent number: 10079283
    Abstract: A manufacturing method of a transistor is provided, and the method includes: providing a base; forming a fin-shaped gate on the base; covering the fin-shaped gate with an insulation layer; providing a substrate; forming a partially cured sol-gel on the substrate; inserting the fin-shaped gate into the partially cured sol-gel, so that a portion of the fin-shaped gate is uncovered by the partially cured sol-gel; after inserting the fin-shaped gate into the partially cured sol-gel, curing the partially cured sol-gel; and processing a portion of the partially cured sol-gel not overlapping with the fin-shaped gate to increase conductivity of the portion of the partially cured sol-gel.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 18, 2018
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Hsin Chiao, Wei-Tsung Chen
  • Patent number: 10079192
    Abstract: A semiconductor chip package assembly includes a package substrate having a chip mounting surface; a plurality of solder pads disposed on the chip mounting surface; a first dummy pad and a second dummy pad spaced apart from the first dummy pad disposed on the chip mounting surface; a solder mask on the chip mounting surface and partially covering the solder pads, the first dummy pad, and the second dummy pad; a chip package mounted on the chip mounting surface and electrically connected to the package substrate through a plurality of solder balls on respective said solder pads; a discrete device having a first terminal and a second terminal disposed between the chip package and the package substrate; a first solder connecting the first terminal with the first dummy pad and the chip package; and a second solder connecting the second terminal with the second dummy pad and the chip package.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: September 18, 2018
    Assignee: MediaTek Inc.
    Inventors: Ching-Wen Hsiao, Tzu-Hung Lin, I-Hsuan Peng, Tung-Hsien Hsieh, Sheng-Ming Chang
  • Patent number: 10076039
    Abstract: A method of fabricating a packaging substrate includes following steps: providing a carrier board having two opposite surfaces, forming on each of the surfaces a plurality of first metal bumps; covering the carrier board and the first metal bumps with a first dielectric layer that has a plurality of first intaglios which exposes a top surface and side surface of the first metal bumps; forming a conductive seedlayer on the first dielectric layer and the first metal bumps; forming a metal layer on the conductive seedlayer; removing a portion of the metal layer and the conductive seedlayer that is higher than the top surface of the first dielectric layer, and forming a first circuit layer in the first intaglios; forming a built-up structure on the first circuit layer and the first dielectric layer, forming a pair of upper and lower entire packaging substrates.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: September 11, 2018
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Chung-W. Ho