Abstract: To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a resistive memory device is provided. The resistive memory device comprises a substrate, and an active region having resistance properties that can be modified to store one or more data bits, the active region comprising region of the substrate with a chemically altered reduction level to establish a resistive memory property in the substrate. The resistive memory device comprises terminals formed into the substrate and configured to couple the active region to associated electrical contacts.

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The channel region is separated a first distance from a first portion of the first type region. The semiconductor device includes a gate region surrounding the channel region. A first portion of the gate region is separated a second distance from the first portion of the first type region. The second distance is greater than the first distance.

Abstract: Tunneling field effect transistors and fabrication methods thereof are provided, which include: an integrated circuit device which includes a circuit input configured to receive an input voltage and a circuit output configured to deliver an output current. The integrated circuit also includes a circuit element having at least one tunneling field effect transistor (TFET). The circuit element connects the circuit input to the circuit output and is characterized by a V-shaped current-voltage diagram. The V-shaped current-voltage diagram describes the relationship between the input voltage of the circuit input and the output current of the circuit output.

Abstract: Method for forming an interconnect structure, comprising the steps of: forming a recessed structure in a dielectric material on a substrate; at least partially filling said recessed structure with a metal chosen from the group consisting of copper, nickel and cobalt; introducing the substrate in a CVD reactor; bringing the substrate in the CVD reactor to a soak temperature and subsequently performing a soak treatment by supplying a germanium precursor gas to the CVD reactor at the soak temperature, thereby substantially completely converting the metal in the recessed structure to a germanide.

Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes: a substrate having a plurality of conductive lands and a plurality of bonding pads surrounding the conductive lands formed on a surface thereof; a plurality of passive devices mounted on the conductive lands; an insulation layer formed on the surface and having a portion of the passive devices embedded therein; a semiconductor chip mounted on a top surface of the insulation layer; a plurality of bonding wires electrically connecting the semiconductor chip and the bonding pads; an encapsulant formed on the surface of the substrate to encapsulate the insulation layer, the bonding wires and the semiconductor chip, wherein a region of the semiconductor chip projected onto the substrate covers a portion of an outermost one of the passive devices. Therefore, the mounting density of the passive devices is improved.

Abstract: A semiconductor device and an electronic device are improved in performances by supporting a large current. An emitter terminal protrudes from a first side of a sealing body, and signal terminals protrude from a second sides of the sealing body. Namely, the side of the sealing body from which the emitter terminal protrudes and the side of the sealing body from which the signal terminals protrude are different. More particularly, the signal terminals protrude from the side of the sealing body opposite the side thereof from which the emitter terminal protrudes. Further, a second semiconductor chip including a diode formed therein is mounted over a first surface of a chip mounting portion in such a manner as to be situated between the emitter terminal and the a first semiconductor chip including an IGBT formed therein in plan view.

Abstract: According to an exemplary implementation, a field-effect transistor (FET) includes first and second gate trenches extending to a drift region of a first conductivity type. The FET also includes a base region of a second conductivity type that is situated between the first and second gate trenches. A ruggedness enhancement region is situated between the first and second gate trenches, where the ruggedness enhancement region is configured to provide an enhanced avalanche current path from a drain region to the base region when the FET is in an avalanche condition. The enhanced avalanche current path is away from the first and second gate trenches. The ruggedness enhancement region can be of the second conductivity type that includes a higher dopant concentration than the base region. Furthermore, the ruggedness enhancement region can be extending below the first and second gate trenches.

Abstract: A method is disclosed for detecting ground faults in a communications system. The method includes measuring a predetermined number of voltage points; determining if the measured voltage points represent recessive or dominant bits; identifying which of the predetermined number of voltage points represent inter-frame bits and which represent frame data bits based on whether the measured voltage points are recessive or dominant; calculating a maximum average voltage for the inter-frame bits; calculating an average frame voltage for all dominant bits within a frame; determining a high average dominant voltage count based on a number of frames for which the average frame voltage is greater than a high voltage threshold; and determining if a ground fault exists based on the average frame voltage and the high average dominant voltage count.

Abstract: After forming a trench extending through a sacrificial gate layer to expose a surface of a doped bottom semiconductor layer, a diode including a first doped semiconductor segment and a second doped semiconductor segment having a different conductivity type than the first doped semiconductor segment is formed within the trench. The sacrificial gate layer that laterally surrounds the first doped semiconductor segment and the second doped semiconductor segment is subsequently replaced with a gate structure to form a gated diode.

Abstract: A method of forming a semiconductor device structure comprises forming at least one 2D material over a substrate. The at least one 2D material is treated with at least one laser beam having a frequency of electromagnetic radiation corresponding to a resonant frequency of crystalline defects within the at least one 2D material to selectively energize and remove the crystalline defects from the at least one 2D material. Additional methods of forming a semiconductor device structure, and related semiconductor device structures, semiconductor devices, and electronic systems are also described.

Abstract: A memory stack structure including a memory film and a vertical semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a backside blocking dielectric layer is formed in the backside recesses and sidewalls of the memory stack structures. A metallic barrier material portion can be formed in each backside recess. A cobalt metal portion can be formed in each backside recess. Each backside recess can be filled with a portion of a backside blocking dielectric layer, a metallic barrier material portion, a cobalt metal portion, and a metallic material portion including a material other than cobalt.

Abstract: Provided is an ink composition including the following components (A), (B), and (C). The component (A) is an anthracene derivative represented by the following formula (A1). The component (B) is an aromatic amine derivative represented by the following formula (B1) (in the formula (B1), one or more of Ar1 to Ar4 are a heterocyclic group represented by the following formula (B1?)). The component (C) is a solvent represented by the following formula (C1) and having a boiling point of 110° C. or higher and a solubility of 1 wt % or less in water.

Abstract: A pixel structure, a method for manufacturing the same and a display panel are provided. The pixel structure includes: a substrate, an anode layer, a first auxiliary light-emitting layer, a light-emitting layer, a cathode layer and at least one first resistive structure. The light-emitting layer at least includes a first light-emitting portion and a second light-emitting portion, where the first light-emitting portion corresponds to a first sub-pixel, the second light-emitting portion corresponds to a second sub-pixel and a turn-on voltage of the first sub-pixel is greater than that of the second sub-pixel. The at least one first resistive structure is arranged between the first auxiliary light-emitting layer and the cathode layer and arranged in a direction perpendicular to the second light-emitting portion, at least partially overlaps with the second light-emitting portion and does not overlap with the first light-emitting portion.

Abstract: A method for manufacturing a light-emitting element, including steps of: providing a wafer-level element including a wafer and a light-emitting stack on the wafer, wherein the wafer including an upper surface and a bottom surface, and light-emitting stack is formed on the upper surface of the wafer; forming a light-emitting stack on the upper surface of the wafer; cutting the wafer from one of the bottom surface or the top surface of the wafer by a water-jet laser having a first beam size; cutting the wafer from the other one of the bottom surface or the upper surface of the wafer by the water-jet laser having a second beam size; and dividing the wafer-level element wafer and the light-emitting stack into a plurality of light-emitting dies.

Abstract: An organic light-emitting device having low-driving voltage, improved efficiency, and long lifespan includes: a first electrode; a second electrode facing the first electrode; a first layer between the first electrode and the second electrode, the first layer including a first compound; a second layer between the first layer and the second electrode, the second layer including a second compound; and a third layer between the second layer and the second electrode, the third layer including a third compound; wherein the first compound does not include a nitrogen-containing heterocyclic group comprising *?N—*? as a ring forming moiety, and wherein the first compound, the second compound, and the third compound each independently include at least one group selected from groups represented by Formulae A to C:

Abstract: Passivated AlGaN/GaN HEMTs having no plasma damage to the AlGaN surface and methods for making the same. In a first embodiment, a thin HF SiN barrier layer is deposited on the AlGaN surface after formation of the gate. A thick HF/LF SiN layer is then deposited, the thin HF SiN layer and the thick HF/LF Sin layer comprising bi-layer SiN passivation on the HEMT. In a second embodiment, a first thin HF SiN barrier layer is deposited on the AlGaN surface before formation of the gate and is annealed. Following annealing of the first SiN layer, the gate is formed, and a second HF SiN barrier layer is deposited, followed by a thick HF/LF SiN layer, the three SiN layers comprising tri-layer SiN passivation on the HEMT.

Abstract: A ferroelectric memory device may include a semiconductor substrate, a plurality of ferroelectric layers, a source, a drain and a gate. The semiconductor substrate may have a recess. The ferroelectric layers may be formed in the recess. The source may be arranged at a first side of the recess. The drain may be arranged at a second side of the recess opposite to the first side. The gate may be arranged on the ferroelectric layers. The ferroelectric layers may be polarized by different electric fields.

Abstract: One or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a channel, such as an un-doped channel, over a substrate. The semiconductor arrangement comprises a gate, such as a gate-all-around structure gate, around the channel. The semiconductor arrangement comprises an isolation structure, such as a silicon germanium oxide structure, between the gate and the substrate. The isolation structure blocks current leakage into the substrate. Because the semiconductor arrangement comprises the isolation structure, the channel can be left un-doped, which improves electron mobility and decreases gate capacitance.

Abstract: Systems and methods for initiating voltage recovery procedures in a fuel cell system based in part on an estimated specific activity over the life of a fuel cell catalyst are presented. In certain embodiments, SA loss of catalyst and electrochemical surface area loss of a FC system may be estimated. An output voltage of the FC system may be estimated based on the estimated SA loss and the electrochemical surface area loss. An amount of recoverable voltage loss may be determined based on a comparison between the estimated output voltage and a measured output voltage. Based on the determined amount of recordable voltage loss, a FC system control action (e.g., a voltage recovery procedure) may be initiated.

Abstract: The disclosure relates to a method of fabricating a vertical MOS transistor, comprising the steps of: forming, above a semiconductor surface, a conductive layer in at least one dielectric layer; etching a hole through at least the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface; forming a gate oxide on the inner lateral edge of the conductive layer and a bottom oxide on the portion of the semiconductor surface; forming an etch-protection sidewall on the lateral edge of the hole, the sidewall covering the gate oxide and an outer region of the bottom oxide, leaving an inner region of the bottom oxide exposed; etching the exposed inner region of the bottom oxide until the semiconductor surface is reached; and depositing a semiconductor material in the hole.