Patents Examined by Tom Thomas
  • Patent number: 10211338
    Abstract: Integrated circuits including tunnel transistors and methods for fabricating such integrated circuits are provided. An exemplary method for fabricating an integrated device includes forming a lower source/drain region in and/or over a semiconductor substrate. The method forms a channel region overlying the lower source/drain region. The method also forms an upper source/drain region overlying the channel region. The method includes forming a gate structure beside the channel region.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: February 19, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Kiok Boone Elgin Quek
  • Patent number: 10211421
    Abstract: A flexible film structure, a method of manufacturing the flexible film structure, and a flexible display device, the flexible film structure including a base film; and at least one functional hard coating layer on the base film, wherein the functional hard coating layer includes a siloxane polymer having an epoxy group.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: February 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-min Lee, Nam-il Koo
  • Patent number: 10211329
    Abstract: There are disclosed herein various implementations of a charge trapping prevention III-Nitride transistor. Such a transistor may be a III-Nitride high electron mobility transistor (HEMT) including a III-Nitride intermediate body situated over a substrate, a channel layer situated over the III-Nitride intermediate body, and a barrier layer situated over the channel layer. The channel layer and the barrier layer are configured to produce a two-dimensional electron gas (2DEG). In addition, the III-Nitride transistor includes a dielectric layer situated over the barrier layer, a gate coupled to the barrier layer, and a drain electrode and a source electrode each extending through the dielectric layer. The drain electrode makes ohmic contact with one or both of the barrier layer and a charge trapping prevention layer situated between the dielectric layer and the barrier layer.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: February 19, 2019
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Hyeongnam Kim, Mohamed Imam, Alain Charles, Jianwei Wan, Mihir Tungare, Chan Kyung Choi
  • Patent number: 10211374
    Abstract: Embodiments of the invention include a light emitting device including a substrate and a semiconductor structure including a light emitting layer. A first reflective layer surrounds the light emitting device. A wavelength converting element is disposed over the light emitting device. A second reflective layer is disposed adjacent a first sidewall of the wavelength converting element.
    Type: Grant
    Filed: January 2, 2015
    Date of Patent: February 19, 2019
    Assignee: LUMILEDS LLC
    Inventors: April Dawn Schricker, Kim Kevin Mai, Brendan Jude Moran
  • Patent number: 10211043
    Abstract: A stacked film is a stacked film including an oxide film, and a metal film provided on the oxide film, in which the oxide film includes a ZrO2 film of which a main surface is a (001) plane, the metal film includes a Pt film or a Pd film that has a single orientation and of which a main surface is a (001) plane, and a [100] axis of the ZrO2 film and a [100] axis of the metal film are parallel to an interface between the oxide film and the metal film, and the axes of both are parallel to each other.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: February 19, 2019
    Assignee: TDK CORPORATION
    Inventors: Takao Noguchi, Yoshihiko Yano
  • Patent number: 10211273
    Abstract: Provided is a display apparatus, including a substrate; a plurality of pixels that are on the substrate and include at least one display device; a separation area that is on the substrate and between two adjacent pixels from among the plurality of pixels; and a penetrating portion that is in the separation area and penetrates the substrate.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: February 19, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kwanghoon Lee, Mugyeom Kim
  • Patent number: 10211150
    Abstract: A memory structure is provided. The memory structure comprises M array regions and N contact regions. M is an integer ?2. N is an integer ?M. Each array region is coupled to at least one contact region. Each contact region comprises a stair structure and a plurality of contacts. The stair structure comprises alternately stacked conductive layers and insulating layers. Each contact is connected to one conductive layer of the stair structure. Two array regions which are adjacent to each other are spatially separated by two contact regions, which are coupled to the two array regions, respectively.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: February 19, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Shih-Hung Chen
  • Patent number: 10209074
    Abstract: A computer-implemented method for determining position of a mobile device using magnetic beacons including detecting, by a sensor in the mobile device, a magnetic signal having a unique signature associated with a given magnetic beacon; storing location and an associated signature for each of a plurality of magnetic beacons in a data store of the mobile device, where each of the magnetic beacons is assigned a different signature; extracting the unique signature from the magnetic signal; comparing the extracted signature to each of the signatures stored in the data store; identifying a given magnetic beacon from the plurality of magnetic beacons, where signature for the given beacon matches the extracted signature; and retrieving the location for the given magnetic beacon for the data store and correlating location of the mobile device with the location of the given magnetic beacon.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: February 19, 2019
    Assignee: The Regents of The University of Michigan
    Inventors: Arie Sheinker, Mark B. Moldwin
  • Patent number: 10204892
    Abstract: A semiconductor package may be composed of a variety of different types of semiconductor chips of different sizes and support structures stacked within the semiconductor package. Semiconductor chips having a larger chip size may be stacked above smaller semiconductor chips. Smaller chips may be included in a layer of the semiconductor package along with a support structure which may assist supporting upper semiconductor chips, such as during a wire bonding process connecting bonding wires to chip pads of the semiconductor chips above the support structure. Use of different thicknesses of die attach film may allow for a further reduction in height of the semiconductor package.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-young Lee, Joon-young Oh, Sung-wook Hwang, Yeoung-jun Cho
  • Patent number: 10199589
    Abstract: A photoelectric conversion element, including a first electrode, a second electrode, and at least one organic layer being present between the first electrode and the second electrode, in which the organic layer contains at least two kinds of compounds having the same skeletons and different substituents in combination.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: February 5, 2019
    Assignee: TORAY INDUSTRIES, INC.
    Inventors: Masaaki Umehara, Tsuyoshi Tominaga, Jinwoo Kwon
  • Patent number: 10199572
    Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions. A first dielectric layer is provided over the first and second regions of the substrate. The first dielectric layer corresponds to pre-metal dielectric (PMD) or CA level which comprises a plurality of contact plugs in the first and second regions. A first interlevel dielectric (ILD) layer is provided over the first dielectric layer. The first ILD layer accommodates a plurality of metal lines in M1 metal level in the first and second regions and via contact in V0 via level in the first region. A magnetic random access memory (MRAM) cell is formed in the second region. The MRAM cell includes a magnetic tunnel junction (MTJ) element sandwiched between the M1 metal level and CA level.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Yi Jiang, Daxiang Wang, Wei Shao, Juan Boon Tan
  • Patent number: 10192966
    Abstract: A semiconductor device can include a first active pattern on a substrate, the first active pattern including a plurality of first active regions that protrude from the substrate. A second active pattern can be on the substrate including a plurality of second active regions that protrude from the substrate. A first gate electrode can include an upper portion that extends over the first active pattern at a first height and include a recessed portion that extends over the first active pattern at a second height that is lower than the first height of the first gate electrode. A second gate electrode can include an upper portion that extends over the second active pattern at a first height and include a recessed portion that extends over the second active pattern at a second height that is lower than the first height of the second gate electrode.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: January 29, 2019
    Assignee: Samsung Electronics Co., Inc.
    Inventors: Hyunho Jung, Jeongyun Lee, Taesoon Kwon, Kyungseok Min, Geumjung Seong, Bora Lim, A-Reum Ji, Seungsoo Hong
  • Patent number: 10193056
    Abstract: A synthetic antiferromagnetic (SAF) structure for a spintronic device is disclosed and has an FL2/AF coupling/CoFeB configuration where FL2 is a ferromagnetic free layer with intrinsic PMA. In one embodiment, AF coupling is improved by inserting a Co dusting layer on top and bottom surfaces of a Ru AF coupling layer. The FL2 layer may be a L10 ordered alloy, a rare earth-transition metal alloy, or an (A1/A2)n laminate where A1 is one of Co, CoFe, or an alloy thereof, and A2 is one of Pt, Pd, Rh, Ru, Ir, Mg, Mo, Os, Si, V, Ni, NiCo, and NiFe, or A1 is Fe and A2 is V. A method is also provided for forming the SAF structure.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: January 29, 2019
    Assignee: Headway Technologies, Inc.
    Inventors: Robert Beach, Guenole Jan, Yu-Jen Wang, Ru-Ying Tong
  • Patent number: 10177104
    Abstract: Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: January 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Ming-Da Cheng, Mirng-Ji Lii, Meng-Tse Chen, Wei-Hung Lin
  • Patent number: 10177342
    Abstract: A display device includes a substrate, a barrier layer, a transistor, and a first impact buffer layer. The barrier layer is disposed on the substrate. The transistor is disposed on the barrier layer. The first impact buffer layer is disposed between the barrier layer and the transistor. The first impact buffer layer includes a nanostructure. The nanostructure includes pores.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: January 8, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sun Hee Lee, Pil Suk Lee, Ju Chan Park, Young Gug Seol
  • Patent number: 10170407
    Abstract: Some embodiments include a method of providing an electronic device. The method can comprise: providing a first device substrate; providing one or more first active sections over a second side of the first device substrate at a first device portion of the first device substrate; and after providing the first active section(s) over the second side of the first device substrate at the first device portion, folding a first perimeter portion of the first device substrate toward the first device portion at a first side of the first device substrate so that a first edge portion remains to at least partially frame the first device portion. The first edge portion can comprise a first edge portion width dimension smaller than a first smallest cross dimension of one or more pixel(s) of one or more semiconductor device(s) of the first active section(s). Other embodiments of related methods and devices are also disclosed.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: January 1, 2019
    Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY
    Inventors: Joseph Smith, Emmett Howard, Jennifer Blain Christen, Yong-Kyun Lee
  • Patent number: 10163707
    Abstract: Methods for forming a group III-V device structure are provided. A method includes forming a first through via structure penetrating through group III-V compound layers over a front surface of a semiconductor substrate. The method also includes thinning the semiconductor substrate from a back surface of the semiconductor substrate. The method further includes etching the semiconductor substrate from the back surface to form a via hole substantially aligned with the first through via structure. In addition, the method includes etching the semiconductor substrate from the back surface to form a recess extending from a bottom surface of the recess towards the first through via structure. The first through via structure is exposed by the via hole and the recess. The method also includes forming a conductive layer in the via hole and the recess to form a second through via structure connected to the first through via structure.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hong Chang, Hsin-Chih Lin, Shen-Ping Wang, Chung-Cheng Chen, Chien-Li Kuo, Po-Tao Chu
  • Patent number: 10164081
    Abstract: The invention relates to a method for manufacturing a heterojunction transistor (1), said method comprising the steps of: forming an implanted area (8) by ionically implanting magnesium, calcium, zinc, or fluorine in a first gallium nitride semiconductor layer (4), having a hexagonal crystalline structure, in the [0 0 0 1] orientation of said crystalline structure; forming a second semiconductor layer (6) on the first semiconductor layer so as to form an electron gas layer (5) at the interface between the first and second layers; and forming a control gate (75) over the second conductive layer (6) and vertically in line with the implanted area (8).
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: December 25, 2018
    Assignee: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventor: Erwan Morvan
  • Patent number: 10157964
    Abstract: A memory device according to one embodiment includes a resistance change film, an insulating film provided on the resistance change film, a first wiring provided on the insulating film and being not in contact with the resistance change film, and a high resistance film having a higher resistivity than the first wiring. The high resistance film is provided on a side surface of a stacked body including the insulating film and the first wiring, and the high resistance film is electrically connected between the first wiring and the resistance change film.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: December 18, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kiyohito Nishihara
  • Patent number: 10145897
    Abstract: Motor winding fault detection circuits and methods to detect motor winding faults are disclosed. An example fault detection circuit includes a positive sequence voltage calculator to calculate a positive sequence voltage value for a three-phase motor; a positive sequence current calculator to calculate a positive sequence current value for the three-phase motor; an interpolator to calculate an expected negative sequence voltage value based on the positive sequence voltage value, the positive sequence current value, and measured characteristics of the three-phase motor; a negative sequence voltage calculator to calculate a measured negative sequence voltage value for the three-phase motor; and a fault detector to detect that a winding fault exists in the three-phase motor when a difference between the expected negative sequence voltage value and the measured negative sequence voltage value satisfies a threshold.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: December 4, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Stephen John Fedigan