Abstract: A method is presented for forming a semiconductor structure. The method includes forming gate contacts on a semiconductor substrate, forming trench silicide (TS) contacts on the semiconductor substrate, recessing the TS contacts to form a gap region, filling the gap region of the recessed TS contacts with a dielectric, selectively etching the gate contacts to form a first conducting layer, and selectively etching the TS contacts to form a second conducting layer.

Abstract: Techniques are disclosed for using a high resistance layer between a III-V channel layer and a group IV substrate for semiconducting devices, such as metal-oxide-semiconductor (MOS) transistors. The high resistance layer can be used to minimize (or eliminate) current flow from source to drain that follows a path other than directly through the channel. In some cases, the high resistance layer may be a III-V wide bandgap layer. In some such cases, the wide bandgap layer may have a bandgap greater than 1.4 electron volts (eV), and may even have a bandgap greater than 2.0 eV. In other cases, the wide bandgap layer may be partially or completely converted to an insulator through oxidation or nitridation, for example. The resulting structures may be used with planar, finned, or nanowire/nanoribbon transistor architectures to help prevent substrate leakage problems.

Abstract: One-dimensional nanostructures having uniform diameters of less than approximately 200 nm. These inventive nanostructures, which we refer to as “nanowires”, include single-crystalline homostructures as well as heterostructures of at least two single-crystalline materials having different chemical compositions. Because single-crystalline materials are used to form the heterostructure, the resultant heterostructure will be single-crystalline as well. The nanowire heterostructures are generally based on a semiconducting wire wherein the doping and composition are controlled in either the longitudinal or radial directions, or in both directions, to yield a wire that comprises different materials. Examples of resulting nanowire heterostructures include a longitudinal heterostructure nanowire (LOHN) and a coaxial heterostructure nanowire (COHN).

Abstract: A method of forming an array of memory cells comprises forming an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines, and programmable material of individual inner tier memory cells elevationally between the inner tier first lines and the inner tier second lines where such cross. First insulative material is formed laterally between the inner tier second lines to have respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier second lines. Second insulative material is formed elevationally over the first insulative material and laterally between the inner tier second lines. The second insulative material is of different composition from that of the first insulative material.

Abstract: A complementary metal-oxide-semiconductor field-effect transistor comprises a semiconductor substrate, N-type and P-Type field-effect transistors positioned in the semiconductor substrate. Each of the field-effect transistor includes a germanium nanowire, a III-V compound layer surrounding around the germanium nanowire, a potential barrier layer mounted on the III-V compound layer, a gate dielectric layer, a gate, a source region and a drain region mounted on two sides of the gate. The field-effect transistor can produce two-dimensional electron gases and two-dimensional electron hole gases, and enhance the carrier mobility of the complementary metal-oxide-semiconductor field-effect transistor.

Abstract: An optoelectronic component includes a housing that includes a rectangular basic shape with four sides. The sides each merge into one another at a corner point. At least two carrier arms of two contact elements of a lead frame are guided to an edge of the housing. The two carrier arms are arranged on different sides of the housing. The two carrier arms are each at different spacings from the two corner points of the side on which the carrier arms are arranged. The spacings differ at least in the width of a carrier arm.

Abstract: An optoelectronic semiconductor device comprises a substrate; a semiconductor system including a first conductivity layer, a second conductivity layer, and a conversion unit between the first conductivity layer and the second conductivity layer, wherein the first conductivity layer is closer to the substrate than the second conductivity layer is to the substrate, and the second conductivity layer comprises a top surface perpendicular to a thickness direction of the semiconductor system, and in a top view of the semiconductor system, an outline of the first conductivity layer surrounds an outline of the second conductivity layer; a first electrical connector on the first conductivity layer of the semiconductor system; a second electrical connector comprising a shape formed on the second conductivity layer of the semiconductor system; and a contact layer formed on the top surface of the second conductivity layer and having an outer perimeter at an inner side of the outline of the second conductivity layer in th

Abstract: In various embodiments, a method for forming a device may be provided. The method may include forming a contact layer at least partially on a substrate. The method may also include forming a device structure adhered to the contact layer. In addition, the method may include depositing a transfer medium such that the device structure is at least partially covered by the transfer medium. The method may further include solidifying the transfer medium. The method may also include separating the contact layer, the device structure and the transfer medium from the substrate. The contact layer may have a greater adhesion to the device structure than to the substrate.

Abstract: A semiconductor device includes a heat source and a heat detection element which are formed on a semiconductor substrate; and a heat conductive member formed across both of the heat source and the heat detection element, a thermal conductivity of the heat conductive member being higher than a thermal conductivity of the semiconductor substrate, and wherein the heat source, the heat detection element and the heat conductive member are integrated on the semiconductor substrate.

Abstract: A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions, defining high aspect ratio gaps between adjacent fins. A pair of source/drain trench contacts are electrically coupled to the epitaxial semiconductor layers. The source/drain trench contacts comprise a conformal metal layer and a fill metal. The conformal metal layer conforms to the epitaxial semiconductor layers. The fill metal comprises a plug and a barrier layer, wherein the plug fills a contact trench formed above the fins and the conformal metal layer, and the barrier layer lines the plug to prevent interdiffusion of the conformal metal layer material and plug material.

Abstract: The invention provides a semiconductor package with a through silicon via (TSV) interconnect. An exemplary embodiment of the semiconductor package with a TSV interconnect includes a semiconductor substrate, having a front side and a back side. A contact array is disposed on the front side of the semiconductor substrate. An isolation structure is disposed in the semiconductor substrate, underlying the contact array. The TSV interconnect is formed through the semiconductor substrate, overlapping with the contact array and the isolation structure.

Abstract: A semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer. The tri-layered gate-control stack includes a ferroelectric layer disposed on the substrate, a mid-gap metal layer sandwiched between the ferroelectric layer and the substrate, and an anti-ferroelectric layer. The anti-ferroelectric layer is sandwiched between the substrate and the mid-gap metal layer. Alternatively, the ferroelectric layer and the mid-gap metal layer are sandwiched between the anti-ferroelectric layer and the substrate.

Abstract: The light emitting element is provided to comprise: a first conductive type semiconductor layer; a mesa; a current blocking layer; a transparent electrode; a first electrode pad and a first electrode extension; a second electrode pad and a second electrode extension; and an insulation layer partially located on the lower portion of the first electrode, wherein the mesa includes at least one groove formed on a side thereof, the first conductive type semiconductor layer is partially exposed through the groove, the insulation layer includes an opening through which the exposed first conductive type semiconductor layer is at least partially exposed, the first electrode extension includes extension contact portions in contact with the first conductive type semiconductor layer through an opening, and the second electrode extension includes an end with a width different from the average width of the second electrode extension.

Abstract: A radiation image-pickup device includes: a plurality of pixels configured to generate signal charge based on radiation; and a field effect transistor used to read out the signal charge from the plurality of pixels. The transistor includes a first silicon oxide film, a semiconductor layer, and a second silicon oxide film laminated in order from a substrate side, the semiconductor layer including an active layer, and a first gate electrode disposed to face the semiconductor layer, with the first or the second silicon oxide film interposed therebetween, and the first or the second silicon oxide film or both include an impurity element.

Abstract: A semiconductor substrate is provided. Active areas and trench isolation regions are formed. The active areas extend along a first direction. Buried word lines extending along a second direction are formed in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. Buried digit lines extending along a third direction are formed above the buried word lines. An upper portion of the trench isolation region is removed to form an L-shaped recessed area around each of the cell contact areas. The L-shaped recessed area exposes sidewalls of the cell contact areas. An epitaxial silicon growth process is then performed to grow an epitaxial silicon layer from the exposed sidewalls and a top surface of each of the cell contact areas, thereby forming enlarged cell contact areas.

Abstract: A memory array includes a semiconductor substrate having thereon a plurality of active areas and trench isolation regions between the active areas. Buried word lines are disposed in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into three portions including a digit line contact area and two cell contact areas. Buried digit lines are disposed in the semiconductor substrate above the buried word lines. An epitaxial silicon layer extends from exposed sidewalls and a top surface of each of the cell contact areas.

Abstract: In one aspect, an avalanche photodiode, includes an absorber, a first superlattice structure directly connected to the absorber and configured to multiply holes and a second superlattice structure directly connected to the first superlattice structure and configured to multiply electrons. The first and second superlattice structures include III-V semiconductor material. The avalanche photodiode is a dual mode device configured to operate in either a linear mode or a Geiger mode. In another aspect, a method includes fabricating the avalanche diode.

Abstract: A semiconductor device includes a first transistor including a first electrode, a first insulating layer above the first electrode, the first insulating layer having a first side wall, a first oxide semiconductor layer on the first side wall, the first oxide semiconductor layer being connected with the first electrode, a first gate electrode, a first gate insulating layer, and a second electrode above the first insulating layer, the second electrode being connected with the first oxide semiconductor layer; and a second transistor including a third electrode, a fourth electrode separated from the third electrode, a second oxide semiconductor layer between the third electrode and the fourth electrode, the second oxide semiconductor layer being connected with each of the third electrode and the fourth electrode, a second gate electrode, and a second gate insulating layer.

Abstract: A method of fabricating a transistor includes doping non-overlapping first, second, and third wells in a silicon layer of a substrate. The substrate, second and third wells have a first type of conductivity and the first well and silicon layer have a second type of conductivity. First and second insulating layers are thermally grown over the second well between the first well and the third well, and over the third well, respectively. A gate stack is formed over the first insulating layer and the third well. A first source region having the second type of conductivity is formed in the third well. A gate spacer is formed, a fourth well having the first type of conductivity is doped in the third well between the second insulating layer and the gate spacer, a second source region is formed over the fourth well, and a drain is formed in the first well.

Abstract: Disclosed is a photoelectric conversion element for converting light into electric energy, including a first electrode, a second electrode, and at least one organic layer existing therebetween, the organic layer containing a compound represented by the general formula (1): wherein R1 to R4 are alkyl groups, cycloalkyl groups, alkoxy groups, or arylether groups, which may be respectively the same or different; R5 and R6 are halogens, hydrogens, or alkyl groups, which may be respectively the same or different; R7 is an aryl group, a heteroaryl group, or an alkenyl group; M represents an m-valent metal and is at least one selected from boron, beryllium, magnesium, aluminum, chromium, iron, nickel, copper, zinc, and platinum; L is selected from halogen, hydrogen, an alkyl group, an aryl group, and a heteroaryl group; and m is in a range of 1 to 6 and, when m?1 is 2 or more, each L may be the same or different.