Abstract: A chip arrangement is provided. The chip arrangement includes: a first chip electrically connected to the first chip carrier top side; a second chip electrically connected to the second chip carrier top side; and electrically insulating material configured to at least partially surround the first chip carrier and the second chip carrier; at least one electrical interconnect configured to electrically contact the first chip to the second chip through the electrically insulating material; one or more first electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier top side and second chip carrier top side, and one or more second electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier bottom side and second chip carrier bottom side.

Abstract: In a microelectronic package, a first wire bond wire is coupled to an upper surface of a substrate. A first bond mass is coupled to another end of the first wire bond wire. A second wire bond wire is coupled to the upper surface. A second bond mass is coupled to another end of the second wire bond wire. The first and second wire bond wires laterally jut out horizontally away from the upper surface of the substrate for at least a distance of approximately 2 to 3 times a diameter of both the first wire bond wire and the second wire bond wire. The first wire bond wire and the second wire bond wire are horizontal for the distance with respect to being co-planar with the upper surface within +/?10 degrees.

Abstract: A recessed region can be formed on a semiconductor substrate, and peripheral semiconductor devices can be formed on a recessed horizontal surface of the semiconductor substrate. An alternating stack of insulating layers and sacrificial material layers are formed over the semiconductor substrate, and memory stack structures are formed therethrough. Contact openings extending to sacrificial material layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. Electrically conductive via structures extending to electrically conductive electrodes located at different level can be provided with self-aligned insulating liners.

Abstract: Corner rounding of electrically conductive layers in a replacement electrode integration scheme can be alleviated by employing compositionally modulated sacrificial material layers. An alternating stack of insulating layers and compositionally modulated sacrificial material layers can be formed over a substrate. Each of the compositionally modulated sacrificial material layers has a vertical modulation of material composition such that each compositionally modulated sacrificial material layer provides greater resistance to conversion into a silicon-oxide-containing material at upper and lower portions thereof than at a middle portion thereof during a subsequent oxidation process. Bird's beak features can be formed with lesser dimensions, and electrically conductive layers formed by replacement of remaining portions of the sacrificial material layers with a conductive material can have less corner rounding.

Abstract: The invention provides a non-volatile memory and a fabricating method thereof. The non-volatile memory includes a substrate, an embedded-type charge storage transistor, and a selection transistor. The substrate has an opening. The embedded-type charge storage transistor is disposed in the substrate. The embedded-type charge storage transistor includes a charge storage structure and a conductive layer. The charge storage structure is disposed on the substrate in the opening. The conductive layer is disposed on the charge storage structure and fills the opening. The selection transistor is disposed on the substrate at one side of the embedded-type charge storage transistor, wherein the selection transistor includes a metal gate structure. The non-volatile memory has excellent charge storage capacity.

Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer and/or polymer layer disposed over the substrate and a portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to an exposed portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes line having a width greater than the PPI line.

Abstract: A chip electronic component may include an insulating layer formed on a lower portion of a side surface of an internal coil pattern to avoid a direct contact between the internal coil pattern and a magnetic material, thereby preventing a waveform distortion indicating a reduction in inductance at high frequency.

Abstract: A method of manufacturing a pressure sensor is provided. The method includes: providing a substrate, wherein a bottom electrode and a pressure sensing film are disposed on the substrate; forming an etch stop assembly on the pressure sensing film at a location corresponding to a pressure trench; forming a cover layer on the substrate covering the etch stop assembly and the pressure sensing film; forming a mask layer on the cover layer, wherein an opening of the mask layer is formed above the etch stop assembly and exposes a portion of the cover layer at the location corresponding to the pressure trench; etching the cover layer using the mask layer so as to form the pressure trench in the cover layer; removing the etch stop assembly at a bottom of the pressure trench; and removing the mask layer.

Abstract: A composite material for fluorescent quantum dot micro-nano packaging. The composite material comprises fluorescent quantum dots, a mesoporous particle material having a nanometer lattice structure, and a barrier layer, wherein the fluorescent quantum dots are distributed in the mesoporous particle material, and the barrier layer is coated on the outer surface of the mesoporous particle material. In the composite material according to the invention, the quantum dot aggregation can be effectively retarded, with the barrier layer coated on the surface the water-oxygen micromolecule erosion is prevented, the compatibility and stability of the composite fluorescent particles is improved, and the service life of the composite material for fluorescent quantum dot micro-nano packaging is thus greatly improved.

Abstract: A radio frequency (RF) module comprises an electrical reference, or ground, plane to which one or more RF devices disposed on the module are electrically coupled, and may be disposed beneath the RF devices. The reference plane may be segmented as to form one or more segments of the reference plane that are at least partially electrically isolated from surrounding segments or devices. A module may have a plurality of devices disposed thereon, wherein separate, at least partially isolated reference planes, correspond to different devices of the module. The reference plane may be etched or cut to achieve such segmentation.

Abstract: A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions are present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of a interconnection structure in the semiconductor device is reduced.

Abstract: A semiconductor device has a first and second transistors formed on an active region defined by an insulating region. The active region is divided into a first and second portions arranged in a first direction, and into a third and fourth portions interposed between the first portion and the second portion, and provided adjacent to each other in a second direction orthogonal to the first direction. The first transistor is provided in the first and third portions, and the second transistor is provided in the second and fourth portions.

Abstract: A method for manufacturing a semiconductor device includes: a fixing step in which semiconductor chips are mounted on and fixed to predetermined positions on an upper surface of a single starting substrate to form individual substrates; a connection step in which electrodes of the semiconductor chips and of the starting substrate are connected by wires; a sealing step in which on the upper surface of the starting substrate, the resin is potted among the semiconductor chips to seal an entire lateral circumference of each of the semiconductor chip; a bonding step in which a single starting protective cover to form individual protective covers is bonded to a surface of the resin so as to extend the semiconductor chips; and a cutting step in which an assembly of the semiconductor devices formed by bonding the starting protective cover to the starting substrate via the resin is cut to the semiconductor devices.

Abstract: The present disclosure relates to a solid-state imaging element and an electronic device capable of suppressing occurrence of a dark current and acquiring higher image quality. The solid-state imaging element includes a high-concentration diffusion layer configured to serve as a connection portion by which a wiring is connected to a semiconductor substrate, and a junction leak control film formed to cover a surface of the diffusion layer. Also, to connect the wiring to the diffusion layer, a width of an opening formed in an insulation film stacked on the semiconductor substrate is greater than a width of the diffusion layer. Further, in a charge accumulation portion configured to accumulate a charge generated by a photoelectric conversion portion generating the charge according to an amount of received light, the junction leak control film is also used as a capacitor film of the charge accumulation portion.

Abstract: Provided is a technique of securing reliability of a gate insulating film, as much as in a Si power MOSFET, in a semiconductor device in which a semiconductor material having a larger band gap than silicon is used, and which is typified by, for example, an SiC power MOSFET. In order to achieve this object, in the in the SiC power MOSFET, the gate electrode GE is formed in contact with the gate insulating film GOX, and is formed of the polycrystalline silicon film PF1 having the thickness equal to or smaller than 200 nm, and the polycrystalline silicon film PF2 formed in contact with the polycrystalline silicon film PF1, and having any thickness.

Abstract: A method of fabricating a MOSFET with an undoped channel is disclosed. The method comprises fabricating on a substrate a semiconductor structure having a dummy poly gate, dummy interlayer (IL) oxide, and a doped channel. The method further comprises removing the dummy poly gate and the dummy IL oxide to expose the doped channel, removing the doped channel from an area on the substrate, forming an undoped channel for the semiconductor structure at the area on the substrate, and forming a metal gate for the semiconductor structure. Removing the dummy poly gate may comprise dry and wet etch operations. Removing the dummy IL oxide may comprise dry etch operations. Removing the doped channel may comprise anisotropic etch operations on the substrate. Forming an undoped channel may comprise applying an epitaxial process to grow the undoped channel. The method may further comprise growing IL oxide above the undoped channel.

Abstract: A semiconductor device includes a first substrate, a second substrate stacked over the first substrate, and a pillar member extending obliquely between the first and second substrates. The first substrate includes a mounting surface on which a semiconductor chip is mounted, with a resin interposed between the semiconductor chip and the mounting surface and extending beyond the periphery of the semiconductor chip on the mounting surface. The first substrate further includes a first pad forming part of the mounting surface and disposed outside the resin. The second substrate includes a second pad forming part of its surface facing toward the mounting surface. The second pad at least overlaps the resin when viewed in a direction in which the second substrate is stacked over the first substrate. The pillar member has first and second ends joined to the first and second pads, respectively, to electrically connect the first and second substrates.

Abstract: According to one embodiment, a semiconductor device includes an n-type semiconductor layer, a first electrode, and a nitride semiconductor layer. The n-type semiconductor layer includes diamond. The nitride semiconductor layer is provided between the n-type semiconductor layer and the first electrode. The nitride semiconductor layer includes AlxGa1?xN (0?x?1) and is of n-type.

Abstract: A light emitting diode module structural and a manufacturing method thereof are disclosed. The manufacturing method includes the steps as follows. A base and a light emitting diode die are provided. The light emitting diode die may include a first semiconductor layer and a second semiconductor layer. The light emitting diode die is disposed on the base. A buffer layer is formed to cover the light emitting diode die. A first opening and a second opening are formed on the first semiconductor layer and the second semiconductor layer, respectively. The second opening exposes the second semiconductor layer by penetrating the first semiconductor layer. A conductive pattern layer is formed on the buffer layer, and is electrically connected with the first semiconductor layer and the second semiconductor layer via the first opening and the second opening, respectively.

Abstract: An optoelectronic circuit for producing an optical clock signal that includes an optical thyristor, a waveguide structure and control circuitry. The waveguide structure is configured to split an optical pulse produced by the optical thyristor such that a first portion of such optical pulse is output as part of the optical clock signal and a second portion of such optical pulse is guided back to the optical thyristor to produce another optical pulse that is output as part of the optical clock signal. The control circuitry is operably coupled to terminals of the optical thyristor and receives first and second control signal inputs. The control circuitry is configured to selectively decrease frequency of the optical clock signal based on the first control signal input and to selectively increase frequency of the optical clock signal based on the second control signal input.