Abstract: A method is presented for reducing element segregation of a phase change material (PCM). The method includes forming a bottom electrode, constructing a layered stack over the bottom electrode, the layered stack including the PCM separated by one or more electrically conductive and chemically stable materials, and forming a top electrode over the layered stack. The PCM is Ge—Sb—Te (germanium-antimony-tellurium or GST) and the one or more electrically conductive and chemically stable materials are titanium nitride (TiN) segments.

Abstract: A magnetic tunnel junction with perpendicular magnetic anisotropy (PMA MTJ) is disclosed wherein a free layer interfaces with a tunnel barrier and has a second interface with an oxide layer. A lattice-matching layer adjoins an opposite side of the oxide layer with respect to the free layer and is comprised of CoXFeYNiZLWMV or an oxide or nitride of Ru, Ta, Ti, or Si, wherein L is one of B, Zr, Nb, Hf, Mo, Cu, Cr, Mg, Ta, Ti, Au, Ag, or P, and M is one of Mo, Mg, Ta, Cr, W, or V, (x+y+z+w+v)=100 atomic %, x+y>0, and each of v and w are >0. The lattice-matching layer grows a BCC structure during annealing thereby promoting BCC structure growth in the oxide layer that results in enhanced free layer PMA and improved thermal stability.

Abstract: The present disclosure provides an array substrate, a method for preparing the same, and a display device. The method includes: forming a metal layer on a base substrate; coating a photoresist on the metal layer; exposing the photoresist by a mask plate in such a manner that an amount of light acting on a first photoresist portion is less than that of light acting on a second photoresist portion to form a first photoresist reserved portion located and a second photoresist reserved portion located; after etching off the metal portion, stripping the first photoresist reserved portion and the second photoresist reserved portion, to obtain the first metal pattern located in the fan-out area and the second metal pattern located in the display area, in which a period size of the first metal pattern being smaller than a period size of the second metal pattern.

Abstract: A laminated seed layer stack with a smooth top surface having a peak to peak roughness of 0.5 nm is formed by sequentially sputter depositing a first seed layer, a first amorphous layer, a second seed layer, and a second amorphous layer where each seed layer may be Mg and has a resputtering rate 2 to 30X that of the amorphous layers that are TaN, SiN, or a CoFeM alloy. A template layer that is NiCr or NiFeCr is formed on the second amorphous layer. As a result, perpendicular magnetic anisotropy in an overlying magnetic layer that is a reference layer, free layer, or dipole layer is substantially maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The laminated seed layer stack may include a bottommost Ta or TaN buffer layer.

Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

Abstract: A method for making an integrated device that includes a plurality of planar MOSFETs, includes forming a plurality of doped body regions in an upper portion of a silicon carbide substrate composition and a plurality of doped source regions. A first contact region is formed in a first source region and a second contact region is formed in a second source region. The first and second contact regions are separated by a JFET region that is longer in one planar dimension than the other. The first and second contact regions are separated by the longer planar dimension. The JFET region is bounded on at least one side corresponding to the longer planar dimension by a source region and a body region in conductive contact with at least one contact region.

Abstract: A display apparatus including a substrate including a display area and a non-display area adjacent to the display area, a thin film encapsulation layer disposed on the substrate and including at least one inorganic encapsulation layer and at least one organic encapsulation layer, a touch unit disposed on the thin film encapsulation layer in the display area, and including a first insulating layer and a second insulating layer disposed on the first insulating layer, the second insulating layer having a first opening at least partially exposing the first insulating layer, a first partition wall disposed on the thin film encapsulation layer in the non-display area along a periphery of the display area, and an organic layer covering the touch unit, directly contacting an upper surface of the first insulating layer through the first opening, and extending to the first partition wall.

Abstract: A method of forming a metal chalcogenide material. The method comprises introducing a metal precursor and a chalcogenide precursor into a chamber, and reacting the metal precursor and the chalcogenide precursor to form a metal chalcogenide material on a substrate. The metal precursor is a carboxylate of an alkali metal, an alkaline earth metal, a transition metal, a post-transition metal, or a metalloid. The chalcogenide precursor is a hydride, alkyl, or aryl precursor of sulfur, selenium, or tellurium or a silylhydride, silylalkyl, or silylaryl precursor of sulfur, selenium, or tellurium. Methods of forming a memory cell including the metal chalcogenide material are also disclosed, as are memory cells including the metal chalcogenide material.

Abstract: An antenna apparatus comprises a semiconductor die in a molding compound layer, a first through via is between a sidewall of the semiconductor die and a sidewall of the molding compound layer and an antenna structure over the molding compound layer, wherein a first portion of the antenna structure is directly over a top surface of the semiconductor die and a second portion of the antenna structure is directly over a top surface of the first through via.

Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and a first interconnect structure coupled to the integrated circuit die. Through-vias are also coupled to the first interconnect structure. A molding material is disposed around the integrated circuit die and the through-vias over the first interconnect structure. The molding material has a pit disposed therein. A recovery material is disposed within the pit in the molding material. A second interconnect structure is disposed over the molding material, the recovery material, the integrated circuit die, and the through-vias.

Abstract: A ferroelectric semiconductor device and method are described herein. The method includes performing a diffusion anneal process to drive elements of a dopant film through an amorphous silicon layer and into a gate dielectric layer over a fin to form a doped gate dielectric layer with a gradient depth profile of dopant concentrations. The doped gate dielectric layer is crystallized during a post-cap anneal process to form a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer. A metal gate electrode is formed over the crystallized gate dielectric layer to obtain a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel. The ferroelectric transistor may be used in deep neural network (DNN) applications.

Abstract: A display device, includes: a pixel connected to a scan line and a data line crossing the scan line, wherein the pixel includes a light emitting element, a driving transistor configured to control a driving current supplied to the light emitting element according to a data voltage received from the data line, and a first switching transistor configured to apply the data voltage of the data line to the driving transistor according to a scan signal applied to the scan line; wherein the driving transistor includes a first active layer including an oxide semiconductor and a first oxide layer on the first active layer and including an oxide semiconductor; and wherein the first switching transistor includes a second active layer on the first active layer and including the same oxide semiconductor as the first oxide layer.

Abstract: A light-emitting device includes an epitaxial structure, and first and second electrodes. The epitaxial structure has a first surface and a second surface opposite to each other, first dislocation density regions and second dislocation density regions. The first dislocation density regions and the second dislocation density regions are alternately disposed between the first surface and the second surface. A dislocation density of each first dislocation density region is lower than a dislocation density of each second dislocation density region and a quantity of the first dislocation density regions is at least ten. The epitaxial structure further includes a light-emitting layer, a first-type semiconductor layer and a second-type semiconductor layer disposed on two opposite sides of the light-emitting layer. The first electrode and the second electrode are electrically connected to the first-type semiconductor layer and the second-type semiconductor layer, respectively.

Abstract: The present disclosure is directed to semiconductor structures with source/drain epitaxial stacks having a low-melting point top layer and a high-melting point bottom layer. For example, a semiconductor structure includes a gate structure disposed on a fin and a recess formed in a portion of the fin not covered by the gate structure. Further, the semiconductor structure includes a source/drain epitaxial stack disposed in the recess, where the source/drain epitaxial stack has bottom layer and a top layer with a higher activated dopant concentration than the bottom layer.

Abstract: The semiconductor device includes a first conductor and a second conductor; a first insulator to a third insulator; and a first oxide to a third oxide. The first conductor is disposed to be exposed from a top surface of the first insulator. The first oxide is disposed over the first insulator and the first conductor. A first opening reaching the first conductor is provided in the first oxide. The second oxide is disposed over the first oxide. The second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region. The third oxide is disposed over the second oxide. The second insulator is disposed over the third oxide. The second conductor is disposed over the second insulator. The third insulator is disposed to cover the first region and the second region and to be in contact with the top surface of the first insulator.

Abstract: A MOSFET includes a substrate having a body region of a first conductivity type. A main field effect transistor (mainFET) and a mirror device are formed in the substrate. The mainFET includes first gate trenches, first source regions of a second conductivity type adjacent to the first gate trenches, and first body implant regions of the first conductivity type extending into the body region adjacent to and interposed between the first source regions. The mirror device includes second gate trenches, second source regions of the second conductivity type adjacent to the second gate trenches, second body implant regions of the first conductivity type extending into the body region adjacent to and interposed between the second source regions, and link elements of the first conductivity type interconnecting pairs of the second body implant regions.

Abstract: A perpendicular spin orbit torque (SOT) memory device includes an electrode having a spin orbit coupling material and a perpendicular magnetic tunnel junction (pMTJ) device on a portion of the electrode. The pMTJ device includes a free magnet, a fixed magnet and a tunnel barrier layer in between, where at least one of the fixed magnet or the free magnet includes two magnetic layers and a spacer layer comprising tungsten in between.

Abstract: A package structure includes a first substrate, a second substrate, a plurality of dies, a plurality of first conductive elements, and a plurality of second conductive elements. The first substrate has a recessed region. The second substrate is disposed in the recessed region and protrudes from the first substrate. The dies are disposed on the first substrate and the second substrate, such that the second substrate is disposed between the first substrate and the dies. The first conductive elements are disposed between the dies and the first substrate. The dies are electrically connected with the first substrate through the first conductive elements. The second conductive elements are disposed between the dies and the second substrate. The dies are electrically connected with the second substrate through the second conductive elements.

Abstract: A stretchable display device includes a stretchable substrate, at least a portion of which is stretchable in at least one direction, a plurality of light emitting units formed on the stretchable substrate, the light emitting units being spaced apart from each other, the light emitting units each including a pixel electrode, an emission layer, a common electrode, and a common wiring electrode conducted to the common electrode, and a plurality of encapsulations covering and protecting the plurality of light emitting units, respectively.

Abstract: A pSTTM device includes a first electrode and a second electrode, a free magnet between the first electrode and the second electrode, a fixed magnet between the first electrode and the second electrode, a tunnel barrier between the free magnet and the fixed magnet, a coupling layer between the free magnet and the first electrode, where the coupling layer comprises a metal and oxygen and a follower between the coupling layer and the first electrode, wherein the follower comprises a magnetic skyrmion. The skyrmion follower may be either magnetically and electrically coupled to the free magnet to form a coupled system of switching magnetic layers. In an embodiment, the skyrmion follower has a weaker magnetic anisotropy than an anisotropy of the free magnet.