Abstract: A method of manufacturing a variable resistance memory device may include: forming a memory cell including a variable resistance pattern on a substrate; performing a first process to deposit a first protective layer covering the memory cell; and performing a second process to deposit a second protective layer on the first protective layer. The first process and the second process may use the same source material and the same nitrogen reaction material, and a nitrogen content in the first protective layer may be less than a nitrogen content in the second protective layer.

Abstract: An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.

Abstract: A semiconductor package may include: at least one semiconductor chip disposed such that an active surface on which a plurality of chip pads are disposed faces a redistribution conductive layer; a plurality of vertical interconnectors, each with one end connected to a respective chip pad, extending in a vertical direction toward the redistribution conductive layer; a molding layer covering the semiconductor chip and the vertical interconnectors while exposing an other end of each of the vertical interconnectors that is not connected to the chip pad; a plurality of landing pads disposed over the molding layer, and each connected to the other end of each of the vertical interconnectors; a redistribution insulating layer covering the molding layer with an opening that collectively exposes the landing pads; and the redistribution conductive layer that extends over the molding layer and the redistribution insulating layer while being connected to each of the landing pads.

Abstract: The present disclosure provides an ultraviolet LED epitaxial production method and an ultraviolet LED, where the method includes: pre-introducing a metal source and a group-V reactant on a substrate, to form a buffer layer through decomposition at a first temperature; growing an N-doped AlwGa1-wN layer on the buffer layer at a second temperature; growing a multi-section LED structure on the N-doped AlwGa1-wN layer at a third temperature, wherein a number of sections of the multi-section LED structure is in a range of 2 to 50; and each section of the LED structure comprises an AlxGa1-xN/AlyGa1-yN multi-quantum well structure and a P-doped AlmGa1-mN layer, and the multi-section LED structure emits light of one or more wavelengths, which realizes that a single ultraviolet LED emits ultraviolet light of different wavelengths, thereby improving the luminous efficiency of the ultraviolet LED.

Abstract: An organic light-emitting display device includes an anti-peeling pattern. An organic light-emitting element including a pixel electrode, an organic light-emitting layer, and a common electrode is disposed on a substrate. A bank layer is disposed on the pixel electrode so as to expose at least a portion of the pixel electrode. The anti-peeling pattern having at least one delta-shaped space is disposed on the bank layer. The anti-peeling pattern, disposed on the bank layer, minimizes peeling of the encapsulation layer that can be caused by either compressive or tensile stress generated by bending in a flexing environment in which the organic light-emitting display device is used.

Abstract: An organic light-emitting display panel and a manufacturing method thereof and an organic light-emitting display device are provided. The organic light-emitting display panel includes a first light-emitting element, a second light-emitting element, a first color filter layer, a second color filter layer; a color of light emitted by the first light-emitting element is different from a color of light emitted by the second light-emitting element and is same as a color of the first color filter layer, and the color of the light emitted by the second light-emitting element is same as a color of the second color filter layer, a brightness attenuation speed of the light emitted by the first light-emitting element is faster than a brightness attenuation speed of the light emitted by the second light-emitting element; the first color filter layer has a first convex surface; and/or the second color filter layer has a first concave surface.

Abstract: A semiconductor package includes a semiconductor chip with a normal connection electrode and a measurement connection electrode, formed on a first surface, and a substrate with a normal substrate pad, connected to the normal connection electrode, and a measurement substrate pad, connected to the measurement connection electrode. The normal substrate pad and the measurement substrate pad are formed on a surface that faces the first surface. The measurement connection electrode includes first and second edge measurement connection electrodes and first and second center measurement connection electrodes. The measurement substrate pad includes a center measurement substrate pad, a first edge measurement substrate pad, and a second edge measurement substrate pad.

Abstract: An electronic device structure having a shielding structure includes a substrate with an electronic component electrically connected to the substrate. The shielding structure includes conductive spaced-apart pillar structures that have proximate ends connected to the substrate and distal ends spaced apart from the substrate, and that are laterally spaced apart from the first electronic component. In one embodiment, the conductive pillar structures are conductive wires attached at one end to the substrate with an opposing end extending away from the substrate so that the conductive wires are provided generally perpendicular to the substrate. A package body encapsulates the electronic component and the conductive spaced-apart pillar structures. In one embodiment, the shielding structure further includes a shielding layer disposed adjacent the package body, which is electrically connected to the conductive spaced-apart pillar structures. In one embodiment, the electrical connection is made through the package.

Abstract: A semiconductor device comprises: a nitride semiconductor layer; an oxide insulating film formed to contact the nitride semiconductor layer; and a gate electrode formed to contact the oxide insulating film and made of metal nitride in a crystal orientation including at least one of the (200) orientation and the (220) orientation.

Abstract: Disclosure herein relates to a unit pixel structure incorporating multiple photodiodes is disclosed. The unit pixel is formed in a semiconductive stack. The unit pixel includes a sensor well region, a floating diffusion region, a first gate structure and a second gate structure. The first gate structure is disposed over the semiconductive stack and the second gate structure extends into the semiconductive stack.

Abstract: A method comprises applying a metal-paste printing process to a surface-mount device to form a metal pillar, placing a first semiconductor die adjacent to the surface-mount device, forming a molding compound layer over the first semiconductor die and the surface-mount device, grinding the molding compound layer until a top surface of the first semiconductor die is exposed and forming a plurality of interconnect structures over the molding compound layer.

Abstract: A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top fin surface, an upper fin side surface portion adjacent to the top fin surface, and a lower fin side surface contiguously connected to the upper fin side surface portion. The lining oxide layer peripherally encloses the lower fin side surface portion of the semiconductor fin. The silicon nitride based layer is disposed conformally over the lining oxide layer. The gate oxide layer is disposed conformally over the top fin surface and the upper fin side surface portion.

Abstract: An array substrate provided. Since arranging a second metal layer into a grid structure, the grid structure and a constant voltage signal trace disposed on a third metal layer are connected in parallel, and a storage capacitor is used as a connection point for the grid structure. The grid structure ensures a high pixel density and also reduces voltage drop, thereby improving brightness uniformity. Moreover, in the manufacturing process, the grid structure and the second metal layer can be formed simultaneously, thereby eliminating a need for additional processes and saving cost.

Abstract: A single memory cell array is formed to maintain current delivery and mitigate current spike through the deposition of resistive materials in two or more regions of the array, including at least one region of memory cells nearer to contacts on the conductive lines and at least one region of memory cells farther from the contacts, where the contacts connect the conductive lines to the current source. Higher and lower resistive materials are introduced during the formation of the memory cells and the conductive lines based on the boundaries and dimensions of the two or more regions using a photo mask. Multiple memory cell arrays formed to maintain current delivery and mitigate current spike can be arranged into a three-dimensional memory cell array. The regions of memory cells in each memory cell array can vary depending on resistance at the contacts on the conductive lines that provide access to the memory cells, where the resistance can vary from one memory cell array to another.

Abstract: A display panel comprises a first substrate; a second substrate; a display region; an encapsulation region disposed at a periphery of the display region; an encapsulation layer disposed at the encapsulation region and between the first and second substrates; and a reflective layer disposed at the encapsulation region and between the first substrate and the encapsulation layer. The reflective layer includes a first reflective region and a second reflective region configured to satisfy one of the following: in a first direction, a gap between the first and second reflective regions is greater than or equal to a first predetermined distance, the first direction being from the display region to the encapsulation region, and in a second direction, a gap between the first and second reflective regions is greater than or equal a second predetermined distance, the second direction being parallel to the first substrate and perpendicular to the first direction.

Abstract: The present invention provides a semiconductor device comprising (a) a semiconductor substrate, (b) a gate trench portion provided from an upper surface of the semiconductor substrate into the semiconductor substrate and extends on an upper surface of the semiconductor substrate in a predetermined extending direction, (c) a gate insulating film provided on an inner wall of the gate trench portion, (d) an interlayer dielectric film provided above the semiconductor substrate; and (e) a protective insulating film, which is, in contact with the gate insulating film, provided between the interlayer dielectric film and the gate trench portion in the depth direction of the semiconductor substrate, and is made of a different material from the interlayer dielectric film and the gate insulating film.

Abstract: A semiconductor device includes a plurality of semiconductor patterns that are sequentially stacked and spaced apart from each other on a substrate, and a gate electrode on the plurality of semiconductor patterns. The gate electrode includes a capping pattern and a work function pattern that are sequentially stacked on the plurality of semiconductor patterns. The capping pattern includes a first metal nitride layer including a first metal element, and a second metal nitride layer including a second metal element whose work function is greater than a work function of the first metal element. The first metal nitride layer is disposed between the second metal nitride layer and the plurality of semiconductor patterns. The first metal nitride layer is thinner than the second metal nitride layer.

Abstract: A MESFET transistor on a horizontal substrate surface with at least one wiring layer on the substrate surface. The transistor comprises source, drain and gate electrodes which are at least partly covered by a semiconducting channel layer. The source, drain and gate electrodes optionally comprise interface contact materials for changing the junction type between each electrode and the channel. The interface between the source electrode and the channel is an ohmic junction, the interface between the drain electrode and the channel is an ohmic junction, and the interface between the gate electrode and the channel is a Schottky junction. The substrate is a CMOS substrate.

Abstract: Technologies relating to RRAM-based crossbar array circuits with increase temperature stability are disclosed. An example apparatus includes: a bottom electrode; a filament forming layer formed on the bottom electrode; and a top electrode formed on the filament forming layer, wherein the filament forming layer is configured to form a filament within the filament forming layer when applying a switching voltage upon the filament forming layer, and wherein a material of the filament includes nitrogen-doped Ta2O5, Ta2N/Ta2O5, or TaNyOz.

Abstract: A connecting structure of a conductive layer includes a first conductive layer, a first insulating layer disposed on the first conductive layer and including a first opening overlapping the first conductive layer, a connecting conductor disposed on the first insulating layer and connected to the first conductive layer through the first opening, an insulator island disposed on the connecting conductor, a second insulating layer disposed on the first insulating layer and including a second opening overlapping the connecting conductor and the insulator island, and a second conductive layer disposed on the second insulating layer and connected to a connecting electrode through the second opening. A sum of a thickness of the first insulating layer and a thickness of the second insulating layer is greater than or equal to 1 ?m, and each of the thicknesses of the first and second insulating layers is less than 1 ?m.