Abstract: An organic light-emitting display device including an encapsulating layer and an encapsulating substrate disposed on the encapsulating layer is provided. The encapsulating layer may cover a light-emitting element. The encapsulating substrate may include a material having high thermal conductivity. A reinforcing member may overlap the light-emitting element between the encapsulating layer and the encapsulating substrate. Thus, in the organic light-emitting display device, the rigidity of the encapsulating substrate may be complemented by the reinforcing member. Thereby, the organic light-emitting display device may prevent damage of the light-emitting element due to external impact.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The electrically conductive layers include aluminum and silicon and provide low resistance electrically conductive paths as word lines of the three-dimensional memory device. The aluminum-based electrically conductive layers can provide low resistivity, low mechanical stress, and thermal stability for use as high performance word lines.

Abstract: According to one embodiment, a display device includes an insulating substrate including a first surface, and a second surface opposite to the first surface, a circuit board mounted on the first surface, a supporting member adhered to the insulating substrate on the second surface, and an antistatic layer located between the insulating substrate and the supporting member.

Abstract: The present invention provides a LTPS TFT substrate and a manufacturing method thereof. The LIPS TFT substrate of the present invention includes a metal layer formed on a channel zone so that the metal layer, a source electrode, and a drain electrode can be used as a mask to form LDD zones in a poly-silicon layer in order to save the mask needed for separately forming the LDD zones; further, due to the addition of the metal layer that is connected to the channel zone of the poly-silicon layer, the electrical resistance of the channel zone can be effectively reduced to increase a TFT on-state current.

Abstract: A semiconductor device including a base region present within a fin semiconductor structure that is present atop a dielectric substrate. An epitaxial emitter region and epitaxial collector region are present on opposing sides and in direct contact with the fin semiconductor structure. An epitaxial extrinsic base region is present on a surface of the fin semiconductor substrate that is opposite the surface of the fin semiconductor structure that is in contact with the dielectric base.

Abstract: A semiconductor chip including a substrate including a plurality of chip areas and a line-shaped scribe area defining the chip areas, an integrated circuit (IC) structure on the chip area, the IC structure including a plurality of transistors and a plurality of stacked wiring structures connected to the transistors, and a warpage protector in the line-shaped scribe area and corresponding to the stacked wiring structures, the warpage protector supporting at least one side of the IC structure may be provided.

Abstract: A display panel is provided. It has N types of sub-pixels, each type emits a different color of light, here N is a positive integer and N3. The panel includes: a matrix of repetitive units arranged, each unit has N-row & N-column sub-pixels. The N sub-pixels in each row or each column emit light of different colors. For each repetitive unit, the N sub-pixels along one diagonal line emits light of the same color, and at least two of the N sub-pixels along another diagonal line emit light of different colors; two adjacent sub-pixels in the same column form one pixel unit, and have shapes which are mirror-symmetrical to each other.

Abstract: An environmental-barrier layer can protect a die or an array of die. A substrate that includes various functional components can be coupled to a porous environmental-barrier layer to form an array of die prior to dividing the array into individual die. The porous environmental-barrier layer can be a layer that includes polymer or fluoropolymer. The porous environmental-barrier layer can also be a filter layer for allowing certain waves to pass through and blocking particles and other debris. The porous environmental-barrier layer can protect each die in the array and the functional components from damage by protecting the die and the functional components from mechanical, electrical, or environmental damage (e.g., contamination by fluid or dust) without impeding a function of the functional components.

Abstract: A display panel includes a substrate, a display element, a plurality of pixels arranged in a matrix, a drive circuit that drives the display element, a switching transistor in each of the plurality of pixels and selectively performs switching on the pixel that is to be caused to emit light, a first drive transistor in each of the plurality of pixels and drives a light-emitting element in the pixel, and a second drive transistor in the drive circuit. The switching transistor that is in each of the plurality of pixels, the first drive transistor that is in each of the plurality of pixels, and the second drive transistor in the drive circuit include oxide semiconductors. The switching transistor in each of the plurality of pixels and the second drive transistor in the drive circuit have a higher mobility than the first drive transistor in each of the plurality of pixels.

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Abstract: A magnetic tunnel junction with perpendicular magnetic anisotropy (PMA MTJ) is disclosed wherein a free layer interfaces with a tunnel barrier and has a second interface with an oxide layer. A lattice-matching layer adjoins an opposite side of the oxide layer with respect to the free layer and is comprised of CoXFeYNiZLWMV or an oxide or nitride of Ru, Ta, Ti, or Si, wherein L is one of B, Zr, Nb, Hf, Mo, Cu, Cr, Mg, Ta, Ti, Au, Ag, or P, and M is one of Mo, Mg, Ta, Cr, W, or V, (x+y+z+w+v)=100 atomic %, x+y>0, and each of v and w are >0. The lattice-matching layer grows a BCC structure during annealing thereby promoting BCC structure growth in the oxide layer that results in enhanced free layer PMA and improved thermal stability.

Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

Abstract: A device structure is formed using a silicon-on-insulator substrate. The device structure includes a first switch and a second switch that are formed within a device layer of the silicon-on-insulator substrate and between a buried insulator layer of the silicon on-insulator substrate and a dielectric layer disposed above and coupled to the device layer. An electrically-conducting connection is located in a first trench extending from the device layer through the buried insulator layer to a trap-rich layer such that the electrically-conducting connection is coupled with a substrate.

Abstract: A method for forming a semiconductor structure is disclosed. A substrate is provided. A pad metal and a fuse metal are formed on the substrate. A liner is formed on the pad metal and on the fuse metal. An etching stop layer is formed on the portion of the liner on the fuse metal. A dielectric layer and a passivation layer are formed on the liner and on the etching stop layer. After defining a pad opening and a fuse opening in the passivation layer, a first etching step is performed to remove the dielectric layer from the pad opening and the fuse opening until the pad metal and the etching stop layer are exposed. Afterward, a second etching step is performed to remove the exposed etching stop layer from the fuse opening until the liner on the fuse metal is exposed.

Abstract: To stabilize programming operation and to reduce leakage current. A variable resistance element according to the present invention is provided with: an interlayer insulating film; a first electrode that is formed within the interlayer insulating film and comprises an active electrode, the side surface and the bottom surface of which are covered by a barrier metal; a variable resistance film that is formed on the upper surface of the first electrode; a second electrode that is formed on the variable resistance film; and an insulating film spacer that is formed between the variable resistance film and the barrier metal which covers the side surface of the first electrode. In this connection, the variable resistance film and the barrier metal which covers the side surface of the first electrode are in contact with the insulating film spacer, respectively.

Abstract: A light-emitting device includes a substrate including a substrate second upper surface provided between a substrate bottom surface and a substrate first upper surface in a height direction. A light-emitting element to emit ultraviolet light is provided on the substrate first upper surface. A protective element includes a protective element upper surface provided between the substrate first upper surface and the substrate second upper surface in the height direction. A frame is bonded to the substrate first upper surface via adhesive members to surround the light-emitting element. The frame includes a frame lower surface opposite to the substrate first upper surface and the substrate second upper surface in the height direction to provide a gap between the substrate first upper surface and the frame lower surface. A space in which the light-emitting element is provided communicates with an outside of the light-emitting device via the gap.

Abstract: A perpendicular STT-MRAM comprises apparatus, a method of operating and a method of manufacturing a spin-torque magnetoresistive memory and a plurality of magnetoresistive memory element having a recording layer which has an interface interaction with an underneath dielectric functional layer. The energy switch barrier of the recording layer is reduced under an electric field applying along a perpendicular direction of the functional with a proper voltage on a digital line from a control circuitry; accordingly, the perpendicular magnetization of the recording layer is readily reversible in a low spin-transfer switching current.

Abstract: A thin film transistor (TFT) includes a scan line on a substrate, the scan line including a straight portion extending along a first direction, an active layer including an oxide semiconductor and overlapping the straight portion of the scan line, the active layer having a first region, a second region, and a third region that are linearly and sequentially aligned along the first direction, a first insulating layer between the active layer and the scan line, a first electrode connected to the first region of the active layer, and a second electrode connected to the third region of the active layer.

Abstract: A device structure with a backside contact includes a silicon-on-insulator substrate including a device layer, a buried insulator layer, and an electrically-conducting connection in a trench. A final substrate is connected to the buried insulator layer such that the electrically-conducting connection contacts the final substrate.

Abstract: A method of manufacturing a light emitting element mounting base member includes: arranging a plurality of core members each including an electrical conductor core and a light-reflecting insulating member provided on a surface of the electrical conductor core; cutting the arranged core members to form a base member preparatory body including at least one cut surface on which at least one of the electrical conductor cores and the insulating members are exposed; and insert molding by placing the base member preparatory body in a set of mold, and injecting a light blocking resin composition into the set of mold such that at least one of the electrical conductor cores or at least one metal film formed on at least one of the electrical conductor cores are exposed on at least one outer surface of the light emitting element mounting base member.