Abstract: Methods and structures formed thereby are described relating to the doping non-planar fin structures. An embodiment of a structure includes a substrate, wherein the substrate comprises silicon, a fin on the substrate comprising a first portion and a second portion; and a dopant species, wherein the first portion comprises a first dopant species concentration, and the second portion comprises a second dopant species concentration, wherein the first dopant species concentration is substantially less than the second dopant species concentration.

Abstract: The independent claims of this patent signify a concise description of embodiments. Disclosed is technology, roughly described, in which a semiconductor structure includes a substrate supporting a column of at least one (and preferably more than one) horizontally-oriented nanosheet transistor, each having a respective channel segment of semiconductor crystalline nanosheet material (preferably silicon or a silicon alloy) sheathed by gate stack material, wherein the channel segments have a diamond cubic crystal structure and are oriented such that the {111} planes are horizontal. Also disclosed is a method for fabricating such a structure, and a corrugated substrate that may be formed as an intermediate product. This Abstract is not intended to limit the scope of the claims.

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Abstract: An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.

Abstract: An organic light emitting display device includes a substrate, a first semiconductor element, a second semiconductor element, a protection electrode, and a light emitting structure. The protection electrode is disposed between the second active layer and the second source electrode and the second drain electrode, and has an opening that exposes a portion of the second active layer and the light emitting structure is disposed on the first and second semiconductor elements.

Abstract: According to embodiments of the present invention, a method of forming a self-aligned contact includes depositing an etch-stop liner on a surface of a gate cap and a contact region. A dielectric oxide layer is deposited onto the etch-stop layer. The dielectric oxide layer and the etch-stop liner are removed in a region above the contact region to form a removed region. A contact is deposited in the etched region.

Abstract: An optoelectronic component includes a light emitter including a multiplicity of segments, wherein each segment of the light emitter includes a multiplicity of image points configured to emit light, and an optical element configured to image light emitted by the light emitter into a target region, light emitted by the individual segments of the light emitter is superimposed in the target region, the optical element is subdivided into a number of segments corresponding to a number of segments of the light emitter, each segment of the optical element is respectively arranged over a segment of the light emitter, and the segments of the optical element are respectively configured as double-sided aspherical lenses.

Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.

Abstract: A light emitting device comprises a first group of one or more LEDs each configured to emit light having a blue color point in the 1931 CIE x,y Chromaticity Diagram, a second group of one or more LEDs each configured to emit light having a cyan or yellow color point in the 1931 CIE x,y Chromaticity Diagram, and a third group of one or more LEDs each configured to emit light having a red color point in the 1931 CIE x,y Chromaticity Diagram.

Abstract: Methods and structures formed thereby are described relating to the doping non-planar fin structures. An embodiment of a structure includes a substrate, wherein the substrate comprises silicon, a fin on the substrate comprising a first portion and a second portion; and a dopant species, wherein the first portion comprises a first dopant species concentration, and the second portion comprises a second dopant species concentration, wherein the first dopant species concentration is substantially less than the second dopant species concentration.

Abstract: According to embodiments of the present invention, a method of forming a self-aligned contact includes depositing an etch-stop liner on a surface of a gate cap and a contact region. A dielectric oxide layer is deposited onto the etch-stop layer. The dielectric oxide layer and the etch-stop liner are removed in a region above the contact region to form a removed region. A contact is deposited in the etched region.

Abstract: A thin film transistor array panel includes a substrate, a first gate electrode on the substrate, a semiconductor layer on the first gate electrode, the semiconductor layer including a drain region, a source region, a lightly doped drain (LDD) region, and a channel region, a second gate electrode on the semiconductor layer, the first gate electrode and the second gate electrode each overlapping the channel region, a control gate electrode that overlaps the LDD region, and a source electrode and a drain electrode respectively connected with the source region and the drain region of the semiconductor layer.

Abstract: A microelectromechanical system (MEMS) device may include a MEMS structure over a first substrate. The MEMS structure comprises a movable element. Depositing a first conductive material over the first substrate and etching trenches in a second substrate. Filling the trenches with a second conductive material and depositing a third conductive material over the second conductive material and the second substrate. Bonding the first substrate and the second substrate and thinning a backside of the second substrate which exposes the second conductive material in the trenches.

Abstract: A method of forming adjacent fin field effect transistor devices is provided. The method includes forming at least two vertical fins in a column on a substrate, depositing a gate dielectric layer on the vertical fins, and depositing a work function material layer on the gate dielectric layer. The method further includes depositing a protective liner on the work function material layer, and forming a fill layer on the protective liner. The method further includes removing a portion of the fill layer to form an opening between an adjacent pair of two vertical fins, where the opening exposes a portion of the protective liner. The method further includes depositing an etch-stop layer on the exposed surfaces of the fill layer and protective liner, forming a gauge layer in the opening to a predetermined height, and removing the exposed portion of the etch-stop layer to form an etch-stop segment.

Abstract: A method produces an optoelectronic lighting device. The device efficiently increases a decoupling of electromagnetic radiation from a volume emitter LED chip. This is achieved in that, a frame made of an optical material is provided on side surfaces of the volume emitter LED chip, wherein the frame has a curved section. Light decoupled via the side surfaces of the volume emitter LED chip is thereby coupled into the frame, and can be decoupled again via same or reflected, for example, on a reflective material applied to the frame.

Abstract: A vertical memory device includes first gate electrodes stacked on a cell region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel extending through the first gate electrodes and extending in the vertical direction, a first contact plug structure contacting a corresponding one of the first gate electrodes, extending in the vertical direction, and including a first metal pattern, a first barrier pattern covering a lower surface and a sidewall of the first metal pattern and a first metal silicide pattern covering a lower surface and a sidewall of the first barrier pattern, and a second contact plug structure extending in the vertical direction on a peripheral circuit region of the substrate and including a second metal pattern and a second barrier pattern covering a lower surface and a sidewall of the second metal pattern.

Abstract: A method of forming a field effect transistor device is provided. The method includes forming a gate stack on a substrate, and forming a sidewall spacer on the gate stack. The method further includes forming a protective liner on the sidewall spacer, and forming a sacrificial gate cap on the gate stack. The method further includes forming a first dielectric fill layer on the protective liner, and forming a second dielectric fill layer on the first dielectric fill layer. The method further includes forming an opening in the second dielectric fill layer and the first dielectric fill layer that exposes the protective liner and sacrificial gate cap. The method further includes removing the sacrificial gate cap to form a cavity between the gate stack and the second dielectric fill layer, and removing the exposed sacrificial liner.

Abstract: Semiconductor structure and method for fabricating a semiconductor structure are provided. A substrate including device regions and an isolation region located adjacent to and between the device regions is provided. A fin on the substrate, gate structures across the fin at the device regions, source/drain doped regions in the fin at two sides of each of the gate structures, and a sacrificial gate across the fin at the isolation region are provided. The sacrificial gate and a portion of the fin near a bottom of the sacrificial gate are removed, thus forming a first opening in the fin. An insulation structure in the first opening is formed. Two sides of the sacrificial gate are in contact with the source/drain doped regions at adjacent device regions. A top surface of the insulation structure is flush with or higher than top surfaces of the source/drain doped regions.

Abstract: An image display device includes a drive circuit substrate, micro LED elements, and a wavelength conversion layer that converts excitation light emitted from the micro LED elements and that emits converted long-wavelength light to a side opposite to the drive circuit substrate, the micro LED elements and the wavelength conversion layer being sequentially stacked on the drive circuit substrate. The micro LED elements include a first multilayer film that reflects the long-wavelength light converted by the wavelength conversion layer.

Abstract: A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate.