Abstract: A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate.

Abstract: Provided is a Group III-V compound semiconductor device. The device includes a substrate, a compound semiconductor layer provided on the substrate; and a buffer layer interposed between the compound semiconductor layer and the substrate. The compound semiconductor layer includes a first semiconductor area having a first conductivity type and a second semiconductor area having a second conductivity type. The buffer layer includes a high electron density area. In the buffer layer, an electron density of the high electron density area is higher than an electron density outside the high electron density area.

Abstract: A vertical semiconductor device includes odd and even cell blocks, and odd and even block pad structures. Each of the odd cell blocks includes first conductive line structures including conductive lines and insulation layers alternatively stacked in a first direction. Each of the even cell blocks includes second conductive line structures having substantially the same shape as the first conductive line structures. The odd block pad structure is connected to first edge portions of the first conductive line structures. The even block pad structure is connected to second edge portions, opposite the first edge portions, of the second conductive line structures. Each of the odd cell blocks and the even cell blocks has a first width in a third direction. Each of the odd and even block pad structures is formed on a region of a substrate having a second width greater than the first width in the third direction.

Abstract: A semiconductor structure includes a substrate, a gate electrode, a first dielectric layer, a gate metal layer, a source structure, and a drain structure. The first dielectric layer has a first opening exposing the gate electrode and a second opening, and the depth of the second opening is greater than the depth of the first opening. The gate metal layer conformally covers the top surface of the first dielectric layer, the first opening, and the second opening to serve as a gate field plate. A first portion of the gate metal layer at the bottom of the first opening is higher than a second portion of the gate metal layer at the bottom of the second opening. The source structure and the drain structure are disposed at opposite sides of the gate structure, wherein the second opening is disposed between the gate electrode and the drain structure.

Abstract: An electronic device includes a substrate; and a pad area on the substrate, the pad area including: a first pad part including a first pad terminal; a second pad part on a side of the first pad part in a first direction and including a second pad terminal; and a third pad part on the other side of the first pad part in the first direction and including a third pad terminal, each of the first pad terminal, the second pad terminal and the third pad terminal including a first long side, a second long side facing the first long side, and at least one bridge extending from the first long side to the second long side, the first long side of the first pad terminal extending in a second direction intersecting the first direction.

Abstract: A MOSFET includes a substrate having a body region of a first conductivity type. A main field effect transistor (mainFET) and a mirror device are formed in the substrate. The mainFET includes first gate trenches, first source regions of a second conductivity type adjacent to the first gate trenches, and first body implant regions of the first conductivity type extending into the body region adjacent to and interposed between the first source regions. The mirror device includes second gate trenches, second source regions of the second conductivity type adjacent to the second gate trenches, second body implant regions of the first conductivity type extending into the body region adjacent to and interposed between the second source regions, and link elements of the first conductivity type interconnecting pairs of the second body implant regions.

Abstract: A package structure includes a first substrate, a second substrate, a plurality of dies, a plurality of first conductive elements, and a plurality of second conductive elements. The first substrate has a recessed region. The second substrate is disposed in the recessed region and protrudes from the first substrate. The dies are disposed on the first substrate and the second substrate, such that the second substrate is disposed between the first substrate and the dies. The first conductive elements are disposed between the dies and the first substrate. The dies are electrically connected with the first substrate through the first conductive elements. The second conductive elements are disposed between the dies and the second substrate. The dies are electrically connected with the second substrate through the second conductive elements.

Abstract: A semiconductor device includes a semiconductor body, first and second electrodes and a control electrode. The semiconductor body is positioned between the first and second electrodes. The control electrode is provided between the semiconductor body and the first electrode. The semiconductor body includes a first layer of a first conductivity-type and a second layer of a second conductivity-type alternately arranged along the first electrode. The first and second layers include first and second low-concentration portions, respectively. The first low-concentration portion has a first conductivity-type impurity concentration lower than that in other portion of the first layer. The second low-concentration portion has a second conductivity-type impurity concentration lower than that in other portion of the second layer. The first low-concentration portion is positioned at a level same as a level of the second low-concentration portion in a direction directed toward the first electrode from the second electrode.

Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.

Abstract: A memory device may be provided that includes: a substrate; a coupling layer which is located on the substrate and has electrical conductivity; a meta-atomic layer which is located on or under the coupling layer; a memory layer which is located on the meta-atomic layer; and an electrode layer which is located on the memory layer and has electrical conductivity. The memory layer is composed of a material which produces spontaneous polarization at a voltage equal to or higher than a predetermined voltage. Through this, the memory device can be electrically driven and can continuously maintain modulated optical characteristics. Also, the memory device according to the embodiment of the present invention can modulate optical characteristics by multiple electrical inputs.

Abstract: A semiconductor apparatus includes: an insulating substrate including an insulating layer having first and second main surfaces, a metal plate on the first main surface, and first to fourth conductors on the second main surface; a semiconductor device including a rear electrode electrically connected to the first conductor and a front electrode electrically connected to the second conductor; a temperature detection device including a first electrode electrically connected to the third conductor and a second electrode electrically connected to the fourth conductor; a first terminal electrically connected to the third conductor; a second terminal positioned so as to be wire-connectable to the fourth conductor; and a third terminal electrically connected to the second conductor, wherein the fourth conductor is positioned so as to be wire-connectable to the second conductor.

Abstract: Provided are a method of manufacturing a semiconductor package substrate, a semiconductor package substrate manufactured using the method of manufacturing a semiconductor package substrate, a method of manufacturing a semiconductor package, and a semiconductor package manufactured using the method of manufacturing a semiconductor package. The method of manufacturing a semiconductor package substrate includes forming first grooves or first trenches in a bottom surface of a base substrate having a top surface and the bottom surface and formed of a conductive material; filling the first grooves or trenches with resin; curing the resin; removing exposed portions of the resin overfilled in the first grooves or trenches; etching the top surface of the base substrate to expose at least portions of the resin filled in the first grooves or trenches; and forming a second groove or a second trench in the bottom surface of the base substrate.

Abstract: A semiconductor device including a chip package and an antenna package disposed on the chip package is provided. The chip package includes a semiconductor chip, an encapsulation enclosing the semiconductor chip, and a redistribution structure disposed on the semiconductor chip and the encapsulation and electrically coupled to the semiconductor chip. The antenna package includes an antenna pattern electrically coupled to the chip package, and an intermediate structure disposed between the antenna pattern and the chip package, wherein the intermediate structure comprises a ceramic element in contact with the redistribution structure and thermally dissipating a heat generated from the semiconductor chip.

Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 ?m2.

Abstract: Methods for forming a semiconductor device structure are provided. The method includes bonding a first wafer and a second wafer, and a first transistor is formed in a front-side of the first semiconductor wafer. The method further includes thinning a front-side of the second wafer and forming a second transistor in the front-side of the second wafer.

Abstract: An integrated device and a method for making said integrated device. The integrated device includes a plurality of planar MOSFETs that have a first contact region formed in a first source region of a plurality of source regions and a second contact region formed in a second source region of the plurality of source regions. The first and second contact regions have respective portions of the source region doped with the second conductivity type, and the first and second contact regions are separated by a JFET region, wherein the JFET region is longer in one planar dimension than the other and the first and second contact regions are separated by the longer planar dimension. The JFET region is bounded on at least one side corresponding to the longer planar dimension by a source region and a body region in conductive contact with at least one contact region.

Abstract: A semiconductor structure includes a decoupling capacitor on a semiconductor substrate. The decoupling capacitor includes a multilayer stack structure having one or more active regions on a top surface thereof. The semiconductor structure further includes one or more semiconductor devices on the one or more active regions on the decoupling capacitor.

Abstract: An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.

Abstract: A method for fabricating a backside contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer. The method includes forming a first switch and a second switch in the device layer. A trench that extends through the device layer and partially through the buried insulator layer is formed. An electrically-conducting connection is formed in the trench.

Abstract: A display device including a substrate including a display area and a non-display area, a common electrode line in the non-display area, and a protective layer coating at least a part of an end portion of the common electrode line.