Abstract: A semiconductor device of an embodiment includes a first GaN-based semiconductor layer, a second GaN-based semiconductor layer provided on the first GaN-based semiconductor layer and having a larger bandgap than the first GaN-based semiconductor layer, a source electrode provided on the second GaN-based semiconductor layer, a drain electrode provided on the second GaN-based semiconductor layer, a recess provided between the source electrode and the drain electrode in the second GaN-based semiconductor layer, a gate insulating film provided on a surface of the recess, and a gate electrode provided on the gate insulating film and having an end portion in a gate width direction, located in the recess.

Abstract: A photodetection device includes: a photoelectric converter generating charge; a first transfer channel having first and second ends, the first end being connected to the photoelectric converter, charge from the photoelectric converter being transferred from the first end toward the second end; a second transfer channel diverging from the first transfer channel at a first position; a third transfer channel diverging from the first transfer channel at a second position, further than the first position from the first end; a first charge accumulator accumulating charge transferred through the second transfer channel; a second charge accumulator accumulating charge transferred through the third transfer channel; a first gate electrode switching between transfer/cutoff of charge in the first transfer channel; and at least one second gate electrode switching between transfer/cutoff of charge in the second and third transfer channels, the third transfer channel being wider than the second transfer channel.

Abstract: A method for fabricating a backside contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer. The method includes forming a first switch and a second switch in the device layer. An electrically-conducting connection is formed in a trench. The handle wafer is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is connected to the buried insulator layer such that the electrically-conducting connection contacts the final substrate.

Abstract: Methods and devices for forming multiple fin lengths includes forming a material stack on vertical fins. A plurality of mandrels are formed on the material stack. Spacers are formed along the plurality of mandrels with the spacers width being a length of short fins. One or more of the plurality of mandrels are removed. The material stack is patterned to form the short fins beneath the spacers and long fins. The vertical fins are cut with the pattern of the material stack to form the short fins and the long fins.

Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, an oxide semiconductor layer, a gate insulating film, a gate electrode, a first insulating film and a second insulating film. The oxide semiconductor layer is provided on the insulating substrate and includes first and second low-resistance regions and a high-resistance region between the first and second low-resistance regions. The gate insulating film is provided on the high-resistance region of the oxide semiconductor layer. The gate electrode is provided on the gate insulating film. The first insulating film is provided above the gate electrode, gate insulating film and first and second low-resistance regions of the oxide semiconductor layer, and contains at least fluorine. The second insulating film is provided on the first insulating film, and contains aluminum.

Abstract: A display unit includes: a display layer including a pixel electrode; a semiconductor layer provided in a layer below the display layer, the semiconductor layer including a wiring layer that includes a material removable by an etchant by which the pixel electrode is also removable; and a terminal section configured to electrically connect the semiconductor layer to an external circuit, the terminal section including a first electrically-conductive layer made of a material same as a material of the wiring layer.

Abstract: A radiation-emitting semiconductor device includes a housing body having a chip mounting area, a chip connection region, a radiation-emitting semiconductor chip, and a light-absorbing material, wherein the radiation-emitting semiconductor chip is fixed to the chip connection region, the chip connection region is covered with the light-absorbing material at selected locations at which the chip connection region is not covered by the radiation-emitting semiconductor chip, the radiation-emitting semiconductor chip is free of the light-absorbing material in selected locations, the housing body has a cavity in which the at least one radiation-emitting semiconductor chip is arranged, the chip mounting area is a surface of the housing body which abuts the cavity, and the chip mounting area is free of the light-absorbing material in selected locations remote from the chip connection region.

Abstract: A method is presented for forming a device having multiple field effect transistors (FETs) with each FET having a different work function. In particular, the method includes forming multiple microchips in which each FET has a different threshold voltage (Vt) or work-function. In one embodiment, four FETs are formed over a semiconductor substrate. Each FET has a source, drain and a gate electrode. Each gate electrode is processed independently to provide a substantially different threshold voltage.

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

Abstract: Disclosed are embodiments of an improved method for forming a vertical field effect transistor (VFET). In each of the embodiments of the method, a semiconductor fin is formed sufficiently thick (i.e., wide) so that the surface area of the top of the semiconductor fin is sufficiently large to facilitate epitaxial growth thereon of a semiconductor material for a second source/drain region. As a result, the second source/drain region will be sufficiently large to avoid potential contact-related defects (e.g., unlanded contacts, complete silicidation of second source/drain region during contact formation, etc.). Additionally, either before or after this second source/drain region is formed, at least the center portion of the semiconductor fin, which will include the channel region of the VFET, is thinned down to a desired critical dimension for optimal VFET performance. Also disclosed are VFET structure embodiments resulting from this method.

Abstract: A semiconductor device includes a plurality of compensation regions of a first conductivity type arranged in a semiconductor substrate. The semiconductor device further includes a plurality of drift region portions of a drift region of a vertical electrical element arrangement. The drift region has a second conductivity type. The drift region portions and the compensation regions are arranged alternatingly. At least portions of a border of a depletion region occurring in a static blocking state of the vertical electrical element arrangement are located within the drift region portions at a depth of less than a depth of at least a subset of the compensation regions.

Abstract: A thin film transistor substrate includes: a substrate; and a first thin film transistor and a second thin film transistor that are disposed on the substrate. The first thin film transistor includes a first gate electrode and a first oxide semiconductor layer that is used as a channel. The second thin film transistor includes a second gate electrode and a second oxide semiconductor layer that is used as a channel. The first oxide semiconductor layer includes a first oxide semiconductor material that is different in mobility from a second oxide semiconductor material that the second oxide semiconductor layer includes.

Abstract: A semiconductor device includes a substrate including first to third fins aligned in a first direction, a first trench arranged between the first fin and the second fin, and a second trench arranged between the second fin and the third fin. The semiconductor device further includes a first field insulating film arranged in the first trench, a second field insulating film formed in the second trench, a first dummy gate arranged on the first field insulating film and a second dummy gate at least partly arranged on the second field insulating film. A lower surface of the second field insulating film is arranged to be lower than a lower surface of the first field insulating film.

Abstract: A semiconductor device comprises a semiconductor substrate; a multilevel wiring layer structure on the semiconductor substrate; and a variable resistance element in the multilevel wiring layer structure, wherein the variable resistance element comprises a variable resistance element film whose resistance changes between a top electrode and a bottom electrode, wherein the multilevel wiring layer structure comprises at least a wiring electrically connected to the bottom electrode and a plug electrically connected to the top electrode, and wherein the wiring also serves as the bottom electrode.

Abstract: According to one embodiment, a display device includes an insulating substrate including a first surface, and a second surface opposite to the first surface, a circuit board mounted on the first surface, a supporting member adhered to the insulating substrate on the second surface, and an antistatic layer located between the insulating substrate and the supporting member.

Abstract: A light-emitting device includes a plurality of light-emitting elements, a phosphorescent phosphor layer including a green phosphorescent phosphor that emits green light and has an afterglow property, and a sealing resin that disperses the green phosphorescent phosphor. The light-emitting device includes a red phosphor that emits red light, a sealing resin that disperses the red phosphor, and a red phosphor layer that contains only a red phosphor as a phosphor. The phosphorescent phosphor layer and the red phosphor layer are disposed apart from each other, and the light-emitting device emits white light while electric current is supplied to the plurality of light-emitting elements, and emits green light after ending the supply of the electric current to the light-emitting elements.

Abstract: A laminated seed layer stack with a smooth top surface having a peak to peak roughness of 0.5 nm is formed by sequentially sputter depositing a first seed layer, a first amorphous layer, a second seed layer, and a second amorphous layer where each seed layer may be Mg and has a resputtering rate 2 to 30× that of the amorphous layers that are TaN, SiN, or a CoFeM alloy. A template layer that is NiCr or NiFeCr is formed on the second amorphous layer. As a result, perpendicular magnetic anisotropy in an overlying magnetic layer that is a reference layer, free layer, or dipole layer is substantially maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The laminated seed layer stack may include a bottommost Ta or TaN buffer layer.

Abstract: A vertical semiconductor device includes odd and even cell blocks, and odd and even block pad structures. Each of the odd cell blocks includes first conductive line structures including conductive lines and insulation layers alternatively stacked in a first direction. Each of the even cell blocks includes second conductive line structures having substantially the same shape as the first conductive line structures. The odd block pad structure is connected to first edge portions of the first conductive line structures. The even block pad structure is connected to second edge portions, opposite the first edge portions, of the second conductive line structures. Each of the odd cell blocks and the even cell blocks has a first width in a third direction. Each of the odd and even block pad structures is formed on a region of a substrate having a second width greater than the first width in the third direction.

Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? epi layer, a p-well, vertical insulated gate electrodes formed in the p-well, and n+ regions between the gate electrodes, so that vertical npn and pnp transistors are formed. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gate electrodes, referenced to the cathode. To speed up the removal of residual electrons in the p-well after the gate electrode voltage is removed, a p+ region is added adjacent the n+ regions, and an n-layer is added below the p+ region. The cathode electrode directly contacts the p+ region and the n+ regions. During turn-off, the p+ region provides holes which recombine with the residual electrons to rapidly terminate the current flow.

Abstract: A semiconductor device includes an SOI substrate having a base substrate material, an active semiconductor layer positioned above the base substrate material and a buried insulating material layer positioned between the base substrate material and the active semiconductor layer. A gate structure is positioned above the active semiconductor layer and a back gate region is positioned in the base substrate material below the gate structure and below the buried insulating material layer. An isolation region electrically insulates the back gate region from the surrounding base substrate material, wherein the isolation region includes a plurality of implanted well regions that laterally contact and laterally enclose the back gate region and an implanted isolation layer that is formed below the back gate region.