Abstract: A method for fabricating a backside contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer. The method includes forming an electrically-conducting connection in a trench. The handle wafer is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is connected to the buried insulator layer such that the electrically-conducting connection contacts the final substrate.

Abstract: An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.

Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and a first interconnect structure coupled to the integrated circuit die. Through-vias are also coupled to the first interconnect structure. A molding material is disposed around the integrated circuit die and the through-vias over the first interconnect structure. The molding material has a pit disposed therein. A recovery material is disposed within the pit in the molding material. A second interconnect structure is disposed over the molding material, the recovery material, the integrated circuit die, and the through-vias.

Abstract: The invention relates to a Micro Organic Opto-Electronic device emitting a light impulse having a time response below 10 ns, in response to an electrical impulse having a pulse duration time below 100 ns, comprising a dielectric substrate (61, 131) which supports: at least one ground plane (121a, 121b); a first planar electrode (62, 71, 171); an organic layer stack (67, 72, 135) partially covering said first planar electrode (A, 62); a second planar electrode (63, 73, 173) with at least a part covering said organic layer stack (135) and said first planar electrode (62, 71, 171); defining an active area (45, 54, 64, 74) of the Organic Opto-Electronic device; some electrical wires for the voltage supply connected to the first planar electrode (62, 71, 171) and to the second planar electrode (63, 73, 173); the first planar electrode (62, 71, 171), the second planar electrode (63, 73, 173) and the ground plane (121a, 121b) are separated by gaps (132, G, h) without conductive material, the gaps (132, G, h) ha

Abstract: A laminated seed layer stack with a smooth top surface having a peak to peak roughness of 0.5 nm is formed by sequentially sputter depositing a first seed layer, a first amorphous layer, a second seed layer, and a second amorphous layer where each seed layer may be Mg and has a resputtering rate 2 to 30X that of the amorphous layers that are TaN, SiN, or a CoFeM alloy. A template layer that is NiCr or NiFeCr is formed on the second amorphous layer. As a result, perpendicular magnetic anisotropy in an overlying magnetic layer that is a reference layer, free layer, or dipole layer is substantially maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The laminated seed layer stack may include a bottommost Ta or TaN buffer layer.

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a gate electrode, and a first memory structure. The semiconductor channel layer is disposed on the substrate. The gate electrode and the first memory structure are disposed on the semiconductor channel layer. The first memory structure includes a first bottom plate, a first top plate, and a first memory element layer. The first top plate is disposed on the first bottom plate. The first memory element layer is disposed between the first bottom plate and the first top plate. The first bottom plate contacts the semiconductor channel layer. Purposes of process simplification and/or memory density enhancement may be achieved by integrating a transistor with a memory structure.

Abstract: A semiconductor device comprises a multi-layered structure disposed over a substrate (101) and defining a composite lateral etch profile. The multi-layered structure includes a lower sub-layer (105-1) disposed over the substrate (101) and comprising a metal oxide material that includes indium and zinc, the indium and zinc content in the lower sub-layer (105-1) substantially defining a first indium to zinc content ratio; a middle sub-layer (105-2) disposed over the lower sub-layer (105-1) and comprising a metal material; an upper sub-layer (105-3) disposed over the middle sub-layer (105-2) and comprising a metal oxide material that includes indium and zinc, the indium to zinc content in the upper sub-layer (105-3) substantially defining a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and a lateral byproduct layer formed over the lateral etched surface, comprising substantially an metal oxide of the metal material in the middle sub-layer (105-2).

Abstract: Provided are semiconductor devices and fabricating methods thereof. The semiconductor device includes a field insulating layer formed in a substrate, an interlayer dielectric layer formed on the field insulating layer and including a trench exposing at least a portion of the field insulating layer, a deposition insulating layer formed in the trench to be disposed on the field insulating layer, a gate insulating layer formed the trench to be disposed on the deposition insulating layer, and a metal gate formed the trench on the gate insulating layer.

Abstract: An electronic device structure includes a leadframe with a die pad and a lead. A semiconductor die is mounted adjacent to the die pad. A clip having a clip tail section is attached to the lead. The clip further has a clip top section attached to the clip tail section, and the clip top section is attached to a die top side of the semiconductor die with a conductive material. The clip further has an opening disposed to extend through the clip top section. In one embodiment, after a reflow step the conductive material forms a conductive fillet at least partially covering sidewall surfaces of the opening, and has a height within the opening with respect to a bottom surface of the clip top section. The opening and the conductive fillet provide an improved approach to monitoring coverage of the conductive material between the clip top section and the die top side of the semiconductor die.

Abstract: A method of forming a semiconductor structure is disclosed. A substrate is provided with a pad metal and a fuse metal formed thereon. A liner and an etching stop layer are formed at least covering a top surface of the fuse metal. A dielectric layer is formed on the substrate and a passivation layer is formed over the dielectric layer. A pad opening and a fuse opening are defined in the passivation layer. A first etching step is performed to remove the dielectric layer from the pad opening and the fuse opening to expose a top surface of the pad metal from the pad opening and an upper surface of the etching stop layer from the fuse opening respectively. A second etching step is performed to remove the etching stop layer from the fuse opening until an upper surface of the liner is exposed.

Abstract: A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate.

Abstract: A microelectromechanical system (MEMS) device may include a MEMS structure over a first substrate. The MEMS structure comprises a movable element. Depositing a first conductive material over the first substrate and etching trenches in a second substrate. Filling the trenches with a second conductive material and depositing a third conductive material over the second conductive material and the second substrate. Bonding the first substrate and the second substrate and thinning a backside of the second substrate which exposes the second conductive material in the trenches.

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface, a first insulation isolation film in which a first trench is formed and a conductive film having a gate electrode, a first buried part buried in the first trench and a first cap part located on the first buried part. The semiconductor substrate has a source region, a drain region, a drift region and a body region. The gate electrode faces the body region which is sandwiched between the drift region and the source region while being insulated from the body region. The first cap part projects longer than the first buried part in a channel width direction which is a direction along a boundary between the body region and the drift region in a planar view on the first insulation isolation film.

Abstract: A display device including a substrate including a display area and a non-display area, a common electrode line in the non-display area, and a protective layer coating at least a part of an end portion of the common electrode line.

Abstract: A magnetic tunnel junction with perpendicular magnetic anisotropy (PMA MTJ) is disclosed wherein a free layer interfaces with a tunnel barrier and has a second interface with an oxide layer. A lattice-matching layer adjoins an opposite side of the oxide layer with respect to the free layer and is comprised of CoXFeYNiZLWMV or an oxide or nitride of Ru, Ta, Ti, or Si, wherein L is one of B, Zr, Nb, Hf, Mo, Cu, Cr, Mg, Ta, Ti, Au, Ag, or P, and M is one of Mo, Mg, Ta, Cr, W, or V, (x+y+z+w+v)=100 atomic %, x+y>0, and each of v and w are >0. The lattice-matching layer grows a BCC structure during annealing thereby promoting BCC structure growth in the oxide layer that results in enhanced free layer PMA and improved thermal stability.

Abstract: Disclosed herein is a display device in which light emitting elements of a plurality of colors including a light emitting element emitting blue light are formed in each pixel on a substrate on which a transistor is formed for each sub-pixel, and a plurality of pixels formed with sub-pixels of the plurality of colors as a unit are arranged in a form of a matrix, wherein relative positional relation between transistors of sub-pixels of respective light emission colors including blue light and a light emitting section of a light emitting element emitting the blue light is laid out such that distances between the transistors of the sub-pixels of the respective light emission colors including the blue light and the light emitting section of the light emitting element emitting the blue light are equal to each other for the respective colors.

Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 ?m2.

Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate; forming an initial metal layer; simultaneously forming a plurality of discrete first metal layers and openings by etching the initial metal layer; forming a plurality of sidewalls covering the side surface of the first metal layers; and forming a plurality of second metal layers to fill the openings.

Abstract: A method is presented for forming a device having multiple field effect transistors (FETs) with each FET having a different work function. In particular, the method includes forming multiple microchips in which each FET has a different threshold voltage (Vt) or work-function. In one embodiment, four FETs are formed over a semiconductor substrate. Each FET has a source, drain and a gate electrode. Each gate electrode is processed independently to provide a substantially different threshold voltage.

Abstract: A method of forming a metal chalcogenide material. The method comprises introducing a metal precursor and a chalcogenide precursor into a chamber, and reacting the metal precursor and the chalcogenide precursor to form a metal chalcogenide material on a substrate. The metal precursor is a carboxylate of an alkali metal, an alkaline earth metal, a transition metal, a post-transition metal, or a metalloid. The chalcogenide precursor is a hydride, alkyl, or aryl precursor of sulfur, selenium, or tellurium or a silylhydride, silylalkyl, or silylaryl precursor of sulfur, selenium, or tellurium. Methods of forming a memory cell including the metal chalcogenide material are also disclosed, as are memory cells including the metal chalcogenide material.