Abstract: An example apparatus comprises an array of memory cells coupled to sensing circuitry. The apparatus can include a control component configured to cause computing of a data value equal to a logical OR between the digit of a mask and a data value stored in a memory cell located in a row at a column of the array corresponding to a digit of a vector stored in the array. The control component can cause storing of the data value equal to the logical OR in the memory cell located in the row at the column of the array corresponding to the digit of the vector.

Abstract: A method of operating a memory device including a first memory block having a plurality cell strings is provided. Each of the plurality of cell strings includes a string selection transistor connected in series to a first dummy cell, a plurality of normal cells, a second dummy cell and a ground selection transistor. The method includes programming the first dummy cell, and programming the normal cells in at least one of the cell strings after the programming the first dummy cell. The normal cells are selected based on a first program command inputted to the memory device. The programming the first dummy cell is performed at least twice before the normal cells are programmed. A number of times of programming the first dummy cell is different according to a level of a voltage applied to the first dummy cell and a level of a voltage applied to the normal cells.

Abstract: In one embodiment, a memory system is provided comprising at least one memory die, a sensor configured to sense an average amount of power consumed by the memory system over a time period, and a controller. The controller is configured to maintain a token bucket that indicates an amount of power currently available for memory operations in the at least one memory die and is further configured to reduce a number of tokens in the token bucket by an amount of power consumed over the time period as indicated by the average amount of power sensed by the sensor over the time period.

Abstract: Provided are an apparatus, memory controller and method for performing a block erase operation with respect to a non-volatile memory. A command is generated to perform a portion of the block erase operation. At least one read or write operation is performed after executing the command. An additional instance of the command is executed in response to determining that the block erase operation did not complete after performing the at least one read or write operation.

Abstract: A device is disclosed that includes a driver, a sinker, a memory column, a reference column, a reference resistor and a sensing unit. At least one of the driver and the sinker has a trimmable resistance. For write operation, one of resistive memory cells is conducted based on a row location in the memory column thereof, the driver provides a write current flowing therethrough and the trimmable resistance is trimmed based on the row location. For read operation, the sensing unit senses a read current of the memory column and a reference current of the reference column and the reference resistor when one of the resistive memory cells and a positionally corresponding one of the reference bit cells are conducted.

Abstract: A semiconductor memory device may include: a data alignment signal generation unit suitable for generating an alignment signal corresponding to an input speed of data; a data alignment unit suitable for aligning the data in response to the alignment signal to output aligned data; and a state data storage unit suitable for storing the aligned data in response to a control signal which is activated at a given time.

Abstract: A memory device includes a first memory element provided on a first side of a semiconductor member, the first memory element including a first charge storage layer provided between the first side of the semiconductor member and a first electrode film, the semiconductor member extending to a first direction, the first side of the semiconductor member being along the first direction; a second memory element on a second side of the semiconductor member, the second memory element including a second charge storage layer provided between the second side of the semiconductor member and a second electrode film, the second side being opposed on the first side with the semiconductor member; a cell source line connected to an end of the semiconductor member; and a control unit.

Abstract: An electronic device is disclosed that includes memory cells, a word line, a selection unit and a self-boosted driver. The memory cells are configured to store data. The word line is coupled to the memory cells. The selection unit is disposed at a first terminal of the word line, and is configured to transmit a selection signal to activate the word line according to one of a read command and a write command. The self-boosted driver is disposed at a second terminal of the word line, and is configured to pull up a voltage level of the word line according to a voltage level of the word line and a control signal.

Abstract: A memory device includes memory cell array and an address decoder. The memory cell array includes a normal memory region and a redundant memory region. The normal memory region operates in response to data signal and plurality of normal memory region signals. The redundant memory region operates in response to data signal and plurality of redundant memory region signals. The address decoder includes normal memory region signal generator and redundant memory region signal generator. The normal memory region signal generator activates first normal memory region signals and redundant memory region signal generator activates first redundant memory region signal simultaneously when address decoder operates in test mode. First normal memory region signals correspond to an address signal and are included in plurality of normal memory region signals. A first redundant memory region signal corresponds to an address signal and is included in the plurality of redundant memory region signals.

Abstract: A monolithic three-dimensional memory array is provided that includes global bit lines disposed above a substrate, each global bit line having a long axis, vertically-oriented bit lines disposed above the global bit lines, word lines disposed above the global bit lines, memory cells coupled between the vertically-oriented bit lines and the word lines, and vertically-oriented bit line select transistors coupled between the vertically-oriented bit lines and the global bit lines. Each vertically-oriented bit line select transistor has a width, a first control terminal and a second control terminal. The word lines and the vertically-oriented bit lines have a half-pitch, and the width of the vertically-oriented bit line select transistors is between about two times the half-pitch and about three times the half-pitch. Vertical bit lines disposed above adjacent global bit lines are offset from one another in a direction along the long axis of the global bit lines.

Abstract: Methods are disclosed. In an embodiment of one such method, a method of receiving command signals, the method comprises receiving command signals in combination with a signal provided to a memory address node at a first clock edge and a second clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge and the second clock edge of the clock signal, represents memory commands.

Abstract: A semiconductor device includes a 1st controller suitable for generating refresh control signals for controlling at least two types of refresh operations according to an external refresh signal; and a 2nd controller suitable for controlling the at least two types of refresh operations to be evenly and alternately performed on a plurality of word lines according to the refresh control signals, a predetermined number of times during a unit refresh period corresponding to the external refresh signal.

Abstract: Methods for reading data that was functionally stored include reading a pattern of threshold voltages from a particular group of memory cells, determining which pattern, of a plurality of patterns, matches the read pattern, and determining a group of decoded data associated with the pattern determined to match the read pattern.

Abstract: Non-volatile storage systems, and methods for programming non-volatile storage elements of non-volatile storage systems, are described herein. A method for programming a non-volatile storage element, wherein a loop number is incremented with each program-verify iteration includes performing a plurality of program-verify iterations for the non-volatile storage element. This includes inhibiting programming of the non-volatile storage element when the loop number is less than a loop number threshold corresponding to a target data state that the storage element is being programmed to. This also includes enabling programming of the non-volatile storage element when the the loop number is greater than or equal to the loop number threshold corresponding to the target data state that the storage element is being programmed to.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a memory cell including first and second electrodes and a resistance change film therebetween, and a control circuit controlling a potential difference between the first and second electrodes. The control circuit reversibly changes the memory cell to a first resistive state by applying a first potential to the first electrode and by applying a second potential smaller than the first potential to the second electrode. The control circuit reversibly changes the memory cell to a second resistive state by applying a third potential to the first electrode and by applying a fourth potential smaller than the third potential to the second electrode.

Abstract: Multi-bank SRAM devices, systems, methods of operating multi-bank SRAMs, and/or methods of fabricating multi-bank SRAM systems are disclosed. For example, illustrative multi-bank SRAMs and methods may include or involve features for capturing read and write addresses at a particular frequency, splitting and/or combining them via one or more splitting/combining processes, and bussing them to each SRAM bank, where they may be split and/or combined via one or more splitting/combining processes to read and write to a particular bank. Some implementations herein may also involve features for capturing two beats of write data at a particular frequency, splitting and/or combining them via one or more splitting/combining processes, and bussing them to each SRAM bank, where they may be split and/or combined via one or more splitting/combining processes for writing to a particular bank. Reading and writing to banks may occur at less than or equal to half the frequency of capture.

Abstract: A method controlling the execution of a reliability verification operation in a storage device including a nonvolatile memory device includes; determining whether a read count for a designated unit within the nonvolatile memory device exceeds a count value limit, and upon determining that the read count exceeds the count value limit, executing the reliability verification operation directed to the designated unit, wherein the count value limit is based on at least one of read count information, page bitmap information and environment information stored in the storage device.

Abstract: A content addressable memory device includes a first memory cell having three programmable resistive elements coupled in parallel. The first terminals of the first, second, and third programmable resistive elements are coupled to a first node, the second terminal of the first programmable resistive element coupled to a first source line voltage, the second terminal of the second programmable resistive element coupled to a second source line voltage, and the second terminal of the third programmable resistive element coupled to a first supply voltage. A first access transistor includes a first current electrode coupled to a bit line; a second current electrode coupled to the first node, and a control electrode coupled to a word line. A match line transistor includes a first current electrode coupled to a match line; a second current electrode coupled to a second supply voltage and a control electrode coupled to the first node.

Abstract: An example apparatus includes an address counter configured to provide refresh addresses to a refresh circuit, wherein the address counter includes a plurality of counter cells configured to count through count values between a minimum count value to a maximum count value, wherein an output of each of the plurality of counter cells each corresponds to an address bit of the refresh address, and a reset circuit coupled to a counter cell of the plurality of counter cells, wherein the reset circuit is configured to reset the counter cell of the plurality of counter cells to an initial value responsive to the plurality of counter cells changing from a first count value to a second count value to skip at least some of the count values to provide the refresh addresses, wherein the first and second count values are less than the maximum count value.

Abstract: A semiconductor integrated circuit includes: first and second wiring lines; resistive change memories disposed intersection regions of the first and second wiring lines; and a control circuit controlling the first and second drivers to select one of the first wiring lines and one of the second wiring lines, the control circuit changing a resistance of the selected one of the resistive change memories from the first resistive state to the third resistive state, and then changing the resistive state of the selected one of the resistive change memories from the third resistive state to the second resistive state.