Patents Examined by Trong Phan
  • Patent number: 9489989
    Abstract: A voltage regulator includes an output stage electrically coupled with an output end of the voltage regulator. The output stage includes at least one transistor having a bulk and a drain. At least one back-bias circuit is electrically coupled with the bulk of the at least one transistor. The at least one back-bias circuit is configured to provide a bulk voltage, such that the bulk and the drain of the at least one transistor are reverse biased during a standby mode of a memory array that is electrically coupled with the voltage regulator.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: November 8, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tien Chun Yang, Chih-Chang Lin, Yuwen Swei
  • Patent number: 9490034
    Abstract: Embodiments provide centralized redundancy block repair for memory circuits. Certain embodiments are implemented in context of high-performance memory, such as last-level cache design, where the primary memory bank often uses high-density memory cells (“bitcells”) and supports long self-bitline structures to increase compactness. In such contexts, it can be difficult to finish read operations within a single cycle, even when the entire cache is divided into small bank pieces. Bank-interleaved structure in clusters can be implemented to allow access to different memory banks in consecutive cycles, thereby achieving overall single circle throughput (i.e., the latency can be masked by the interleaving). Accordingly, some embodiments of the centralized block repair can support bank interleaved access, for example, with a strict single-cycle throughput. Some embodiments can also support other features, such as row repair and/or column repair.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: November 8, 2016
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Pangjie Xu, Hoyeol Cho, Ioannis Orginos
  • Patent number: 9489995
    Abstract: A memory device comprises a plurality of sectors and a driving circuit comprising a global word line driver and a first local word line driver. The global word line driver applies an erasing voltage to a selected sector of the sectors via a global word line. The first local word line driver, coupled to the global word line, drives a first local word line of the selected sector with a biasing voltage, so that the first local word line has a first voltage level corresponding to a non-erased state.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: November 8, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Nai-Ping Kuo, Cai-Yun Wu
  • Patent number: 9484074
    Abstract: Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to the cross-coupled p-channel transistors. The load circuit is configured to provide a resistance to control at least in part the loop gain of the current mode sense amplifier, the load circuit including at least passive resistance.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: November 1, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Seong-Hoon Lee, Onegyun Na, Jongtae Kwak
  • Patent number: 9484072
    Abstract: A nonvolatile memory device includes a pair of MIS transistors one of which is placed in a programmed state by a first program operation utilizing a hot carrier effect to store one-bit data in the pair of MIS transistors, and a control unit configured to recall the one-bit data from the pair of MIS transistors in a recall operation, to cause an unprogrammed one of the MIS transistors to be placed in a programmed state by a second program operation utilizing a hot carrier effect in response to the one-bit data recalled from the pair of MIS transistors, and to erase the programmed states of both of the MIS transistors in an erase operation.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: November 1, 2016
    Assignee: NSCore, Inc.
    Inventor: Kenji Noda
  • Patent number: 9478270
    Abstract: Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: October 25, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Eric Lee
  • Patent number: 9479183
    Abstract: A memory storage device having a clock and data recovery circuit module are provided. The module includes sampling circuits, a first logic circuit module, a delay circuit module, a second logic circuit module, a frequency adjustment circuit and a clock control circuit. The sampling circuits sample a data signal according to reference clocks. The first logic circuit module performs a first logic operation according to a sampling result. The delay circuit module delays a result of the first logic operation. The second logic circuit module performs a second logic operation according to said result and the delayed first logic result. The frequency adjustment circuit outputs a frequency adjustment signal according to a result of the second logic operation, and the clock control circuit performs a phase locking accordingly. Therefore, a circuit complexity of the clock and data recovery circuit module may be reduced.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: October 25, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei-Yung Chen, Yu-Chiang Liao
  • Patent number: 9479143
    Abstract: Provided is a semiconductor device including a sequential circuit including a first transistor and a capacitor. The first transistor includes a semiconductor layer including indium, zinc, and oxygen to form a channel formation region. A node electrically connected to a source or a drain of the first transistor and a capacitor becomes a floating state when the first transistor turns off, so that a potential of the node can be maintained for a long period. A power-gating control circuit may be provided to control supply of power supply potential to the sequential circuit. The potential of the node still can be maintained while supply of the power supply potential is stopped.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: October 25, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Jun Koyama
  • Patent number: 9472261
    Abstract: A system and method of refreshing dynamic random access memory (DRAM) are disclosed. A device includes a DRAM, a bus, and a system-on-chip (SOC) coupled via the bus to the DRAM. The SOC is configured to refresh the DRAM at a particular refresh rate based on a temperature of the DRAM and based on calibration data determined based on one or more calibration tests performed while the SOC is coupled to the DRAM.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: October 18, 2016
    Assignee: Qualcomm Incorporated
    Inventors: Dexter Tamio Chun, Jung Pill Kim, Yanru Li
  • Patent number: 9460789
    Abstract: A non-volatile digital memory includes: a plurality of thin film resistors; and a control circuit adapted to: program, during a first programming phase, the thin film resistors with a plurality of bits of data by passing a current through at least one of the thin film resistors to reduce its resistance; and read, during a restoration phase, the plurality of bits of data stored by the thin film resistors by generating an electrical signal associated with each thin film resistor and comparing each electrical signal with a reference signal.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: October 4, 2016
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Vincent Rabary, Nicolas Aupetit
  • Patent number: 9460758
    Abstract: A microelectronic package can include a support element having first and second surfaces and substrate contacts at the first or second surface, zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, and terminals at the second surface electrically coupled with the microelectronic elements. The second surface can have a southwest region encompassing entire lengths of south and west edges of the second surface and extending in orthogonal directions from the south and west edges one-third of each distance toward north and east edges of the second surface, respectively. The terminals can include first terminals at a southwest region of the second surface, the first terminals configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of the memory storage arrays of at least one of the zeroth or first microelectronic elements.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: October 4, 2016
    Assignee: Invensas Corporation
    Inventors: Richard Dewitt Crisp, Yong Chen, Belgacem Haba, Wael Zohni, Zhuowen Sun
  • Patent number: 9460761
    Abstract: A sense amplifier includes: two detection inputs, a latch circuit including two sections coupled to each other and each supplying a data signal. Each section is respectively powered by a P-channel control transistor, having a gate terminal receiving a control signal linked to a respective detection input of the two detection inputs. The sense amplifier includes a control circuit configured to reduce each of the control signals to a sufficiently low voltage to put the corresponding control transistor to the on state, when the control signal reaches a reference voltage. The latch circuit is activated to supply one of the data signals when a corresponding one of the control transistors is in the on state.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 4, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francesco La Rosa
  • Patent number: 9455014
    Abstract: Aspects for adjusting resistive memory write driver strength based on write error rate (WER) are disclosed. In one aspect, a write driver strength control circuit is provided to adjust a write current provided to a resistive memory based on a WER of the resistive memory. The write driver strength control circuit includes a tracking circuit configured to determine the WER of the resistive memory based on write operations performed on resistive memory elements. The write driver strength control circuit includes a write current calculator circuit configured to compare the WER to a target WER that represents the desired yield performance level of the resistive memory. A write current adjust circuit in the write driver strength control circuit is configured to adjust the write current based on this comparison. The write driver strength control circuit adjusts the write current to perform write operations while reducing write errors associated with breakdown voltage.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: September 27, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Kangho Lee, Taehyun Kim, Sungryul Kim, Seung Hyuk Kang, Jung Pill Kim
  • Patent number: 9449692
    Abstract: Methods for functional programming memory cells and apparatuses are disclosed. One such method for functional programming includes encoding a group of data with a function to generate representative data and programming the representative data to the memory. In one embodiment, the representative data is a pattern of threshold voltages to be programmed to a group of memory cells.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: September 20, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Ramin Ghodsi
  • Patent number: 9443588
    Abstract: A resistive memory system, a driver circuit thereof and a method for setting resistances thereof are provided. The resistive memory system includes a memory array, a row selection circuit, a first control circuit and a second control circuit. The memory array has a plurality of resistive memory cells. The row selection circuit is used for activating the resistive memory cells. The first control circuit and the second control circuit are coupled to the resistive memory cells. When each of resistive memory cells is set, the first control circuit and the second control circuit respectively provide a set voltage and a ground voltage to the each of resistive memory cells to form a set current, and the set current is clamped by at least one of the first control circuit and the second control circuit.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: September 13, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Pei-Ling Tseng, Chia-Chen Kuo, Shyh-Shyuan Sheu, Meng-Fan Chang
  • Patent number: 9437319
    Abstract: Provided are methods, devices, and/or the like for reducing the bit line interference when programming non-volatile memory. One method comprises providing a non-volatile memory device comprising a set of cells, each cell associated with a bit line; shooting a programming voltage across each cell; detecting a threshold voltage for each cell; identifying a fast subset of the set of cells and a slow subset of the set of cells based at least in part on the detected threshold voltage for each cell; and shooting the programming voltage until the threshold voltage for each cell is greater than a verify voltage. For each shot a fast bit line bias is applied to the bit line associated each cell of the fast subset and a slow bit line bias is applied to the bit line associated with each cell of the slow subset.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: September 6, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Atsuhiro Suzuki, Ya Jui Lee, Kuan Fu Chen, Chih-Wei Lee
  • Patent number: 9437257
    Abstract: A sensing circuit includes a sensing resistor, a reference resistor and a comparator. The comparator has a first input coupled to the sensing resistor, a second input coupled to the reference resistor, and an output. The first input is configured to be coupled to a data bit line associated with a memory cell to receive a sensing input voltage caused by a cell current of the memory cell flowing through the sensing resistor. The second input is configured to be coupled to a reference bit line associated with a reference cell to receive a sensing reference voltage caused by a reference current of the reference cell flowing through the reference resistor. The comparator is configured to generate, at the output, an output signal indicating a logic state of data stored in the memory cell based on a comparison between the sensing input voltage and the sensing reference voltage.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: September 6, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tien-Chun Yang, Yue-Der Chih, Chan-Hong Chern, Tao Wen Chung
  • Patent number: 9418712
    Abstract: A memory system and method for power management are disclosed. In one embodiment, a memory system is provided comprising at least one memory die, a sensor configured to sense an average amount of power consumed by the memory system over a time period, and a controller. The controller is configured to maintain a token bucket that indicates an amount of power currently available for memory operations in the at least one memory die and is further configured to reduce a number of tokens in the token bucket by an amount of power consumed over the time period as indicated by the average amount of power sensed by the sensor over the time period. Other embodiments are disclosed.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: August 16, 2016
    Assignee: SanDisk Technologies LLC
    Inventor: Eran Erez
  • Patent number: 9412450
    Abstract: Disclosed is a nonvolatile memory having a memory cell array including a plurality of cell strings, each cell string including memory cells stacked in a direction perpendicular to a substrate, a ground selection transistor between the memory cells and the substrate, and a string selection transistor between the memory cells and a bit line. The memory also includes an address decoder connected to the memory cells, the string selection transistors, and the ground selection transistors, and configured to apply a ground voltage to the string selection lines, word lines, and ground selection line. Further, the memory includes a read/write circuit connected to the string selection transistors through bit lines, and at least one first memory cell maintains a threshold voltage higher than a threshold voltage distribution corresponding to an erase state.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: August 9, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gilsung Lee, Jaehoon Jang, Kihyun Kim, Sunil Shim
  • Patent number: 9406390
    Abstract: A method controlling the execution of a reliability verification operation in a storage device including a nonvolatile memory device includes; determining whether a read count for a designated unit within the nonvolatile memory device exceeds a count value limit, and upon determining that the read count exceeds the count value limit, executing the reliability verification operation directed to the designated unit, wherein the count value limit is based on at least one of read count information, page bitmap information and environment information stored in the storage device.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: August 2, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyungryun Kim, Taehoon Kim, Sangkwon Moon