Abstract: A semiconductor memory device has at least one memory cell using a resistance variable element, and a control circuit which controls writing to and reading from the memory cell. Operations by the control circuit include a first writing operation, a second writing operation, and a rewriting operation. The first writing operation is a writing operation for applying a first voltage of a first polarity to the memory cell. The second writing operation is a writing operation for applying a second voltage of a second polarity opposite to the first polarity to the memory cell. The rewriting operation is a writing operation for, when the first writing operation fails, further executing a second A writing operation for applying the second voltage of the second polarity to the memory cell and a first A writing operation for applying the first voltage of the first polarity to the memory cell.

Abstract: A magnetic memory and methods for providing and programming the magnetic memory are described. The memory includes storage cells, magnetic oscillator(s) and bit lines. Each storage cell includes magnetic junction(s) having a free layer, a reference layer, and a nonmagnetic spacer layer between reference and free layers. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The free layer has a first magnetic anisotropy at room temperature and a second magnetic anisotropy at a minimum switching temperature due to at least the write current. The second magnetic anisotropy is not more than ninety percent of the first magnetic anisotropy. The first and second magnetic anisotropies correspond to first and second ferromagnetic resonance (FMR) frequencies. The magnetic oscillator(s) have a frequency range. The first FMR frequency is outside of the frequency range. The second FMR frequency is within the frequency range.

Abstract: A dual-port SRAM timing control circuit, with three NMOS transistors connected in series respectively between ground and nodes of the two bit lines to which the cell structure corresponds. The gates of the NMOS transistors are connected to a corresponding wordline, a pulse signal and a timing control signal, respectively. The each pulse signals are formed by a corresponding clock signal inputted into a first pulse generator, respectively. An address signal, after passing through an address latch, is inputted into an address comparator for comparison, with the address comparison result outputted to a timing control signal generator; and the pulse signal, after undergoing an AND operation, is inputted into the timing control signal generator, with a timing control signal outputted.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for adjusting a voltage level for a write operation on a partially programmed block of a nonvolatile storage device. A write module receives a request to perform a write operation for one or more storage cells of an partially programmed block of a nonvolatile storage device. A characteristic module determines whether a characteristic for a partially programmed block of a nonvolatile storage device satisfies a threshold. A voltage adjustment module adjusts a voltage level applied to one or more source lines connected to the one or more storage cells during a write operation in response to determining a characteristic satisfies a threshold.

Abstract: To provide a semiconductor memory device capable of writing a checkerboard pattern for interference and investigation by three writings regardless of the magnitude of memory capacity by making a change of a simple circuit configuration free from the need of a data holding circuit and a voltage converting circuit large in circuit area in a memory array in which the order of arrangement of bits is reversedly arranged between data words adjacent in a row direction. A row decoder and a column decoder are respectively configured to enable operation switching to an all selection mode and an even/odd-based selection mode in addition to a single address selection mode of a memory array by a control signal from a control circuit.

Abstract: For a non-volatile memory device having a NAND type of architecture, techniques are presented for determining NAND strings that are slow to program, including comparing the amount of current drawn by different sets of memory cells during different write operations. These techniques are particularly applicable to memory devices have a 3D structure, such as of BiCS type, where the slow programming can arise from defects of the spacing between the memory holes, in which the NAND strings are formed, and the local interconnects, such as for connecting common source lines and which run in a vertical direction between groups of NAND strings. The slow to program NAND strings can be recorded and this information can be used when writing data to the NAND strings. Several methods of writing data along a word line that includes such slow to program cells are described.

Abstract: Embodiments include apparatuses, methods, and systems including a circuit which may increase a speed of removal of data stored in a memory cell. In embodiments, the circuit may include a control logic to detect a signal and a boost circuit coupled to the control logic to allow the control logic to disable an operation of the boost circuit in response to detection of the signal. A discharge device may be coupled to the boost circuit to accelerate leakage of a leakage current in response to the detection of the signal. In the embodiment, the leakage current is a leakage current of a memory cell coupled to the discharge device and acceleration of the leakage of the leakage current and the disablement of the operation of the boost circuit may increase a speed of erasure of data in the memory cell. Other embodiments may also be described and claimed.

Abstract: A magnetic memory includes a plurality of memory cells and a data identification circuit. Each of the memory cells includes: a first bias node to which a first voltage is applied in data reading, the first voltage being a positive voltage; a second bias node to which a second voltage is applied in the data reading, the second voltage being a negative voltage having substantially the same absolute value as the first voltage; a connection node; a first spin device element connected between the first bias node and the connection node; and a second spin device element connected between the connection node and the second bias node. The first and second spin device elements operate differentially. The data identification circuit identifies data stored in each of the memory cells based on a polarity of a voltage generated on the connection node.

Abstract: The present invention is provided with: subword drivers SWD for driving subword lines SWL, a selection circuit for supplying either negative potential VKK1 or VKK2 to the subword drivers SWD, and memory cells MC that are selected in the case when the subword line SWL is set to an active potential VPP and are not selected in the case when the subword line SWL is either a negative potential VKK1 or VKK2.

Abstract: Embodiments herein describe DRAM that includes storage circuitry coupled between complementary bit lines which are in turn coupled to the same sense amplifier. The storage circuitry includes a transistor and a storage capacitor coupled in series. The gate of the transistor is coupled to a word line which selectively couples the storage capacitor to one of the complementary bit lines. Because the capacitor is coupled to both of the bit lines, when reading the data stored on the capacitor, the charge on the capacitor causes current to flow from one of the bit lines into the other bit line which causes a voltage difference between the complementary bit lines. Put differently, both ends of the capacitor are electrically coupled to bit lines thereby generating a larger voltage difference between the bit lines when reading data from the storage capacitors.

Abstract: A system includes memory chips mounted on a memory module each having an alert terminal that notifies that the memory chip has detected a predetermined error. The memory module has a first transmission line connected to alert terminals of memory chips, output terminal being connected to one end of the first transmission line, and a first termination resistor having an end connected to another end of the first transmission line. The system further includes a second transmission line having an end connected to the alert terminal and another end connected to a controller and a third transmission line having an end connected to a first input terminal on the memory module and a second end line and a second end having a voltage different from a voltage of another end of the first termination resistor.

Abstract: Provided is a semiconductor device to prevent DC current from flowing between differential input signals. The semiconductor device includes a first input unit configured to buffer a first signal of differential input signals, a second input configured to buffer a second signal of the differential input signals, and a latch coupled between a first repeating node of the first input unit and a second repeating node of the second input unit to prevent duty variation of the first and second signals. The semiconductor device further includes a latch controller configured to selectively switch the operation of the latch based on states of the first and second signals appearing at the first and second repeating nodes during a time interval before preambles of the differential input signals are received.

Abstract: A memory device includes a first memory cell array including memory cells of a single-ended bitline structure, a second memory cell array including memory cells of a single-ended bitline structure, a reference voltage generator configured to output a bitline voltage of a selected one of the first and second memory cell arrays as a sensing voltage according to an array select signal and output a bitline voltage of an unselected memory cell array as a reference voltage, and a differential sense amplifier configured to amplify and output a difference between the sensing voltage and the reference voltage. Logic states of the sensing voltage and the reference voltage are complementary to each other.

Abstract: Clamp elements, memories, apparatuses, and methods for forming the same are disclosed herein. An example memory may include an array of memory cells and a plurality of clamp elements. A clamp element of the plurality of clamp elements may include a cell structure formed non-orthogonally relative to at least one of a bit line or a word line of the array of memory cells and may be configured to control a voltage of a respective bit line.

Abstract: A nonvolatile memory device is provided which includes a page buffer unit. The page buffer unit includes a first page buffer including a first A latch configured to store first upper bit data and a first B latch configured to store first lower bit data, and a second page buffer including a second A latch configured to store second upper bit data and a second B latch configured to store second lower bit data. A set pulse may be applied to both the first A latch and the second B latch, or to both the second A latch and the first B latch. The non-volatile memory device may provide high write performance and may respond within a time out period of a handheld terminal.

Abstract: An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.

Abstract: A method of operating a first voltage regulator includes electrically coupling a transistor of an output stage of the first voltage regulator between a first power voltage and a second power voltage, and reverse biasing a bulk of the transistor by a back-bias circuit during a standby mode of a memory array. The first voltage regulator is coupled to a second voltage regulator and reverse biasing the bulk of the transistor reduces a contention current between the first voltage regulator and the second voltage regulator.

Abstract: An internal voltage generation circuit may include a temperature information generation unit configured to generate a temperature code having a code value corresponding to a temperature. The temperature information generation unit may include a process variation information generation unit configured to generate a process code having a code value corresponding to a process variation. The temperature information generation unit may include a code combination unit configured to generate a combination code in response to a ratio control signal, the temperature code, and the process code. The temperature information generation unit may include an internal voltage generation unit configured to generate an internal voltage having a voltage level corresponding to a code value of the combination code.

Abstract: An array structure includes: a plurality of first signal lines and a plurality of sub-arrays. Each of the sub-array includes: a second signal line, a plurality of third signal lines, a plurality of fourth signal lines, a plurality of local decoders at each intersection of the first signal lines, the second signal line and the third signal lines; and a plurality of array cells at each intersection of the first signal lines, the third signal lines and the fourth signal lines. Respective control terminals of the local decoders are implemented by the first signal lines. In response to a selection status of the first signal lines and the second signal line, one of the local decoders selects one of the third signal lines.

Abstract: In some embodiments, a time division multiplexing (TDM) circuit is configured to receive an external clock signal and generate an internal clock signal that has at least one pulse during a clock cycle of the external clock signal. An address selector is configured to select a current address before a first time within one of the at least one pulse, and select a next address starting from the first time to generate a selected address. An address storage element is configured to receive the selected address from the address selector and provide a passed through or stored address. The provided address is the current address substantially throughout the one of the at least one pulse. A single-port (SP) memory is configured to access at least one SP memory cell at the address provided by the address storage element in response to the internal clock signal.