Patents Examined by Trong Phan
  • Patent number: 9312001
    Abstract: A writing and verifying circuit and a method for writing and verifying a resistive memory thereof are provided. The steps of the method includes: enabling at least one word line signal corresponding to at least one selected resistive memory cell of the resistive memory during a writing and verifying timing period; providing a bit line voltage to the selected resistive memory cells, wherein the bit line voltage continuously increases or decreases from a first voltage level to a second voltage level during the writing and verifying timing period; and, measuring a detected current through the bit line and determining a finish time point of the writing and verifying timing period according to the detected current and a reference current.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: April 12, 2016
    Assignee: Winbond Electronics Corp.
    Inventor: Koying Huang
  • Patent number: 9305637
    Abstract: A nonvolatile semiconductor memory device includes a memory cell array having nonvolatile memory cells in which one of multiple values is programmable therein by setting one of a plurality of threshold values therein and a control circuit that performs a writing operation on the memory cells. The writing operation performed by the control circuit includes a pre-programming verification operation to determine a threshold level of a memory cell in an erasure state, and a program operation in which a program voltage is selected from a plurality of program voltages on the basis of a determination result of the pre-programming verification operation.
    Type: Grant
    Filed: March 2, 2014
    Date of Patent: April 5, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Rieko Funatsuki, Takuya Futatsuyama, Fumitaka Arai
  • Patent number: 9299443
    Abstract: Techniques are provided for more accurately programming memory cells by reducing program noise caused by charge loss in a programming pass in which the number of verify tests varies in different program loops. In an nth program loop, at least one programming characteristic is modified based on the number (N) of data states which were subject to verify tests in the n-1st program loop. For example, a reduced step size or pulse duration, or an elevated bit line voltage (Vbl) can be used. The reduction in the step size or pulse duration, or the increase in Vbl, is proportional to N. The modification of the at least one programming characteristic results in a slowdown of the programming of the memory cells so that program noise is reduced.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: March 29, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Yingda Dong, Liang Pang, Jiahui Yuan
  • Patent number: 9299450
    Abstract: A NAND string includes dummy memory cells between data memory cells and source-side and drain-side select gates. A gradual increase in threshold voltage (Vth) for the dummy memory cells which occurs due to program-erase cycles is detected by read operations at an initial upper checkpoint voltage. If the Vth has increased beyond the checkpoint, the control gate voltage of the dummy memory cells is increased during subsequent programming operations. This maintains a relatively constant channel voltage in an unselected NAND string under the dummy memory cells during a program voltage. Disturbs which can be caused by an increase in a channel voltage gradient are therefore avoided. The dummy memory cells can be periodically read at successively higher checkpoint voltages and the control gate voltage repeatedly increased. If the control gate voltage reaches a maximum allowed level, the dummy memory cells can be erased and reprogrammed.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: March 29, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Liang Pang, Yingda Dong, Zhengyi Zhang
  • Patent number: 9293509
    Abstract: The present invention discloses a small-grain three-dimensional memory (3D-MSG). Each of its memory cells comprises a thin-film diode with critical dimension no larger than 40 nm. The thin-film diode comprises at least a small-grain material, whose grain size G is substantially smaller than the diode size D. The small-grain material is preferably a nano-crystalline material or an amorphous material. The critical dimension f of the small-grain diode is smaller than the critical dimension F of the single-crystalline transistor.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: March 22, 2016
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventors: Guobiao Zhang, Bin Yu, HongYu Yu, Jin He, JinFeng Kang, ZhiWei Liu
  • Patent number: 9286978
    Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a control circuit configured to cause data to be stored in a memory cell by setting the memory cell to be included in one of resistance value distributions. The control circuit is configured to set a first resistance value distribution and a second resistance value distribution, the second resistance value distribution having a resistance value larger than that of the first resistance value distribution, and to set a second width to be larger than a first width, the second width being a width between a second upper limit value of the second resistance value distribution and a second lower limit value of the second resistance value distribution, and the first width being a width between a first upper limit value of the first resistance value distribution and a first lower limit value of the first resistance value distribution.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: March 15, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoichi Minemura, Takayuki Tsukamoto, Takamasa Okawa, Hiroshi Kanno, Atsushi Yoshida
  • Patent number: 9286971
    Abstract: A method and various circuit embodiments for low latency initialization of an SRAM are disclosed. In one embodiment, an IC includes an SRAM coupled to at least one functional circuit block. The SRAM includes a number of storage location arranged in rows and columns. The functional circuit block and the SRAM may be in different power domains. Upon initially powering up or a restoration of power, the functional circuit block may assert an initialization signal to begin an initialization process. Responsive to the initialization signal, level shifters may force assertion of various select/enable signals in a decoder associated with the SRAM. Thereafter, initialization data may be written to the SRAM. Writing initialization data may be performed on a row-by-row basis, with all columns in a row being written to substantially simultaneously.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: March 15, 2016
    Assignee: Apple Inc.
    Inventors: Greg M. Hess, Ramesh Arvapalli, Andrew L. Arengo
  • Patent number: 9281037
    Abstract: Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge of the clock signal, represent a memory command. Furthermore, the signal provided to the memory address node at a second clock edge of the clock signal is not decoded in combination with the received command signals. The memory command may be a reduced power command and/or a no operation command.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: March 8, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Scott Smith, Duc Ho, J. Thomas Pawlowski
  • Patent number: 9275746
    Abstract: A source line floating circuit includes a plurality of floating units. The floating units directly receive decoded row address signals or voltages of word lines as floating control signals, respectively. The decoded row address signals are activated selectively in response to a row address signal. The floating units control electrical connections between source lines and a source voltage in response to the floating control signals in a read operation. Related devices and methods are also described.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: March 1, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Min Jeon, Bo-Young Seo, Tea-Kwang Yu
  • Patent number: 9275719
    Abstract: A voltage regulator includes an amplifier, an output stage coupled with the amplifier, at least one back-bias circuit, and an output end coupled with the output stage and with the amplifier. The output stage includes at least one transistor having a bulk and a drain. The at least one back-bias circuit is coupled with the bulk of the at least one transistor. The output end is configured to be coupled with a memory array and with an output end of another voltage regulator. The back-bias circuit is configured to reduce a contention current between the voltage regulator and the other voltage regulator during a standby mode.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: March 1, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tien Chun Yang, Chih-Chang Lin, Yuwen Swei
  • Patent number: 9275744
    Abstract: A method of enhancing a thermal anneal of a flash memory in an integrated circuit (IC) chip package by addition of an electric field may include heating an integrated circuit (IC) chip, disposed within an IC chip package, to an elevated temperature that does not degrade the IC chip package, where the IC chip includes a flash memory that includes blocks of flash memory cells. A negative electric field may be applied to each of the blocks of flash memory cells at the elevated temperature. The application of the negative electric field and the heating of the IC chip may be terminated. Stored data for each of the blocks of flash memory cells may be retrieved from a storage device and rewritten into each of the blocks of flash memory cells.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: March 1, 2016
    Assignee: International Business Machines Corporation
    Inventors: Eduard A. Cartier, Jeffrey P. Gambino, Adam J. McPadden, Gary A. Tressler
  • Patent number: 9269405
    Abstract: A semiconductor memory includes: a first switching transistor, wherein the first switching transistor has a first terminal, a second terminal, and a third terminal, and the second terminal is coupled to a first word-line; a first differential bit-line pair possessing a non-inverted bit-line and an inverted bit-line, wherein the non-inverted bit-line and the inverted bit-line thereof are mutually-exclusively coupled to the first terminal of the first switching transistor for storing first information; and a second differential bit-line pair possessing a non-inverted bit-line and an inverted bit-line, wherein the non-inverted bit-line and the inverted bit-line thereof are mutually-exclusively coupled to the third terminal of the first switching transistor for storing second information.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: February 23, 2016
    Assignee: MEDIATEK INC.
    Inventor: Chia-Wei Wang
  • Patent number: 9269443
    Abstract: A semiconductor device includes a memory block including even memory cells configured to form an even page and odd memory cells configured to form an odd page. The semiconductor device may also include an operation circuit configured to perform a program operation on the even memory cells and the odd memory cells. A first verify operation may separately verify the even memory cells and the odd memory cells, and a second verify operation may simultaneously verify the even memory cells and the odd memory cells. Further, the operation circuit may be configured to selectively perform the first verify operation and the second verify operation depending on a number of adjacent program fail cells in response to a verify result value.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: February 23, 2016
    Assignee: SK Hynix Inc.
    Inventors: In Geun Lim, Min Kyu Lee, Chi Wook An
  • Patent number: 9268690
    Abstract: A memory device uses a global input/output line or a pair of complementary global input/output lines to couple write data signals and read data signals to and from a memory array. The same input/output line or pairs of complementary global input/output lines may be used for coupling both write data signals and read data signals.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: February 23, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Shigeki Tomishima
  • Patent number: 9263101
    Abstract: A semiconductor memory device includes first and second memory regions configured to store data in a mirrored fashion with respect to each other during a high speed operation period; and a read operation block configured to repeatedly and alternately select the first and second memory regions and read data from a selected memory region, in the case where the first or second memory region is repeatedly selected n read operations of at least two times during the high speed operation period.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: February 16, 2016
    Assignee: SK Hynix Inc.
    Inventor: Kwan-Weon Kim
  • Patent number: 9257971
    Abstract: A semiconductor device includes a first latch, a second latch and a transistor whose semiconductor layer contains an oxide semiconductor. An input of the first latch is electrically connected to one of a source and a drain of the transistor, an output of the first latch is electrically connected to an input of the second latch, and an output of the second latch is electrically connected to the other of the source or the drain of the transistor.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: February 9, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masami Endo, Takuro Ohmaru
  • Patent number: 9245596
    Abstract: A charge pump system includes a logic circuit, a signal processing circuit, a charge pump circuit, a switching circuit, a first controllable discharge path, and a second controllable discharge path. The logic circuit receives a program enabling signal and generates a first control signal. The signal processing circuit receives a pump enabling signal, and generates a second control signal and a third control signal. The charge pump circuit receives the third control signal and generates an output signal. The switching circuit has a control terminal receiving the third control signal, a first terminal connected with the output terminal of the charge pump circuit, and a second terminal connected with a reservoir capacitor. The first controllable discharge path receives the first control signal, and the second controllable discharge path receives the second control signal.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: January 26, 2016
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Cheng-Te Yang
  • Patent number: 9240246
    Abstract: A semiconductor device includes a fuse array with a plurality of fuses, a common signal generation unit suitable for receiving a power-up signal and generating an inverted power-up signal and a reset signal, a plurality of fuse registers suitable for latching a plurality of fuse data for the plurality of fuses and commonly receiving the inverted power-up signal and the reset signal from the common signal generation unit by grouped fuse registers, and an output selection unit suitable for outputting the plurality of fuse data stored on the plurality of fuse registers according to a predetermined sequence.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: January 19, 2016
    Assignee: SK Hynix Inc.
    Inventor: Min-Sik Han
  • Patent number: 9230638
    Abstract: A method includes performing a pre-reading on memory cells selected from a plurality of memory cells according to a pre-read voltage and determining whether the selected memory cells each are read as a first logical value or a second logical value, comparing a number of memory cells read as the first logical value among the selected memory cells with a predetermined number, and when the number of selected memory cells read as the first logical value is smaller than the predetermined number, performing a first main reading of the selected memory cells, the first main reading adapted to read a memory cell that stores multiple bits.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: January 5, 2016
    Assignee: SK HYNIX INC.
    Inventor: Sang Oh Lim
  • Patent number: 9224462
    Abstract: A resistive memory device that simultaneously erases memory cells connected to selected word line(s) included in an erase unit. The erase unit includes fewer word lines than are included in a memory block of the resistive memory device. However, erase verification may nonetheless be performed on a block basis.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: December 29, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: DongHun Kwak, Cheon-An Lee