Patents Examined by Trong Phan
  • Patent number: 9384806
    Abstract: A memory device includes a plurality of memory layers and a selecting circuit configured to select a delta value corresponding to a parameter of at least one of the plurality of memory layers having fabricated thereon at least one memory cell accessed during an operation. The memory device further includes an adjusting circuit configured to adjust an access signal based at least in part on the delta value, the access signal being configured to access the at least one memory cell during the operation.
    Type: Grant
    Filed: August 15, 2015
    Date of Patent: July 5, 2016
    Assignee: Unity Semiconductor Corporation
    Inventors: Christophe Chevallier, Seow Fong Lim, Chang Hua Siau
  • Patent number: 9378815
    Abstract: A resistive memory device includes a memory cell array having a plurality of memory cells therein, which operate in response to word line driving and column selecting signals. Each of memory cells includes a resistive device and a cell transistor connected in series. An I/O sense amplifier senses and amplifies data output from the memory cell array to thereby generate output data, and also generate program current based on input data and provide the program current to the memory cell array. The resistive memory device is also configured to read output data from the I/O sense amplifier and adjust interface states of the cell transistors based on a voltage level of the output data during a test mode.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: June 28, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Kyu Lee, Dae-Won Kim
  • Patent number: 9378775
    Abstract: Such a device is disclosed that includes first and second chips stacked to each other, and a third chip controlling the first and second chips, stacked on the first and second chips, and including first, second and third output circuits. The first output circuit supplies a first command signal to the first chip. The second output circuit supplies the first command signal to the second chip. The third output circuit supplies a second command signal to the first and second chips.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: June 28, 2016
    Assignee: PS4 LUXCO S.A.R.L.
    Inventors: Junichi Hayashi, Homare Sato
  • Patent number: 9367255
    Abstract: A storage device includes a variable resistance memory, a flash memory and a controller. The flash memory includes a plurality of memory cells connected to a plurality of word lines. The controller is configured to receive data from an external device and program the received data in the variable resistance memory or the flash memory according to a quantity of data to be programmed in the flash memory. Further, the controller is configured to read from the variable resistance memory and program the read data in the flash memory, when the quantity of data accumulated in the variable resistance memory corresponds to a super page of data.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: June 14, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Jin Yun, Bogeun Kim
  • Patent number: 9361029
    Abstract: One method for improving the utility of solid-state storage media within a solid state storage device includes referencing one or more storage media characteristics for a set of storage cells of the solid-state storage media. The method also includes determining a configuration parameter for the set of storage cells based on the one or more storage media characteristics. The method includes configuring the set of storage cells to use the determined configuration parameter. The configuration parameter includes a parameter of the set of storage cells modifiable by a module external to the solid-state storage device by way of an interface. The module external to the solid-state storage device includes a device driver executing on a host device.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: June 7, 2016
    Assignee: SANDISK TECHNOLOGIES, INC.
    Inventors: John Strasser, David Flynn, Jeremy Fillingim, Robert Wood, Jea Hyun, Hairong Sun
  • Patent number: 9361985
    Abstract: An operating method of a nonvolatile memory device is provided which includes receiving a command sequence; detecting whether the input command sequence accompanies an impedance calibration operation; and if the input command sequence accompanies the impedance calibration operation, simultaneously performing an operation corresponding to the input command sequence and the impedance calibration operation.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: June 7, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Kim, Soonbok Jang
  • Patent number: 9361989
    Abstract: A memory device comprises a first memory string and a second memory string. The first memory string is coupled to a first bit line and a plurality of word lines, and the second memory string is coupled to a second bit line and the word lines. When an erasing voltage is applied to the word lines, a first voltage is applied to the first bit line to erase data stored in the first memory string, and a second voltage is applied to the second bit line to set the second memory string to be floating.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: June 7, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Kuo-Pin Chang
  • Patent number: 9355723
    Abstract: A semiconductor device may include a controller configured to generate a data retention path control signal in response to a power condition change signal. The semiconductor device may include a plurality of data retention paths configured to sequentially couple a plurality of global input/output (I/O) lines coupled to a volatile memory to a dummy I/O line in response to the data retention path control signal. The semiconductor device may include a dummy I/O pad coupled to the dummy I/O line. The semiconductor device may include a non-volatile memory device coupled to the dummy I/O pad, configured to retain a plurality of storage data received from the volatile memory when the volatile memory is powered off, or provide data retained in the volatile memory as recovery data when power is recovered by the volatile memory.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: May 31, 2016
    Assignee: SK HYNIX INC.
    Inventor: Sangkug Lym
  • Patent number: 9349479
    Abstract: One or more word lines in a Multi Level Cell (MLC) block are identified as being at high risk of read disturb errors and data is selectively copied from such high risk word lines to a location outside the MLC block where the copy is maintained. Subsequent read requests for the data may be directed to the copy of the data outside the MLC block.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: May 24, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Rohit Sehgal, Niles Yang, Abhilash Kashyap
  • Patent number: 9349465
    Abstract: A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes memory cells stacked on a substrate. The method includes applying a reference voltage to an unselected drain select line, applying a drain selection voltage to a selected drain select line, and applying a word line voltage to a normal word line. Before the word line voltage is applied to the normal word line, a positive voltage is applied to a dummy word line to bounce the unselected drain select line.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: May 24, 2016
    Assignee: SK HYNIX INC.
    Inventor: Yoon Soo Jang
  • Patent number: 9349482
    Abstract: A method of programming a nonvolatile memory device is provided which includes applying a program voltage to selected ones of a plurality of memory cells; applying a selected one of a plurality of verification voltages after pre-charging bit lines connected to memory cells to which the program voltage is applied; sensing the memory cells to which the selected verification voltage is applied; selecting memory cells programmed to a target state referring to the sensing result and target state data; and determining whether programming of the selected memory cells is passed or failed.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: May 24, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Suk Kim, Il Han Park, Jung-Ho Song
  • Patent number: 9343158
    Abstract: To program in a nonvolatile memory device include a plurality of memory cells that are programmed into multiple states through at least two program steps, a primary program is performed from an erase level to a first target level with respect to the memory cells coupled to a selected word line A preprogram is performed from the erase level to a preprogram level in association with the primary program with respect to the memory cells coupled to the selected word line, where the preprogram level is larger than the erase level and smaller than the first target level A secondary program is performed from the preprogram level to a second target level with respect to the preprogrammed memory cells coupled to the selected word line.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: May 17, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Ho Song, Su-Yong Kim, Sang-Won Hwang
  • Patent number: 9343151
    Abstract: According to another embodiment, a method of a reset operation for a RRAM is provided. The method includes the following operations: providing a first voltage to the dielectric side electrode of the resistor; and providing a second voltage to a gate of the transistor, wherein the first voltage in a second loop is lower than that in a first loop, and the second voltage in the second loop is higher than that in the first loop.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: May 17, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chun-Yang Tsai, Yu-Wei Ting, Kuo-Ching Huang
  • Patent number: 9343156
    Abstract: Programming techniques for a three-dimensional stacked memory device provide compensation for different intrinsic programming speeds of different groups of memory cells based on the groups' locations relative to the edge of a word line layer. A larger distance from the edge is associated with a faster programming speed. In one approach, the programming speeds are equalized by elevating a bit line voltage for the faster programming memory cells. Offset verify voltages which trigger a slow programming mode by elevating the bit line voltage can also be set based on the group locations. A programming speed can be measured during programming for a row or other group of cells to set the bit line voltage and/or the offset verify voltages. The compensation for the faster programming memory cells can also be based on their speed relative to the slower programming memory cells.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: May 17, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Man L Mui, Yongke Sun, Yingda Dong
  • Patent number: 9343160
    Abstract: Reducing peak current and/or power consumption during erase verify of a non-volatile memory is disclosed. During an erase verify, memory cells are verified at a strict reference level that is deeper (e.g., lower threshold voltage) than a target reference level. After the strict erase verify, strings of memory cells that pass the strict erase verify are locked out from a next erase verify at the target reference level. Locked out strings do not conduct a significant current during erase verify, thus reducing peak current and/or power consumption.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: May 17, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Deepanshu Dutta, Shih-Chung Lee
  • Patent number: 9336841
    Abstract: A device is disclosed that includes a first memory module and a second memory module. The first memory module is configured to output a data signal according to a first phase of a first control signal. The second memory module is connected to the first memory module and includes a latch and a derace latch. The latch is configured to hold a received data signal according to a second phase of a second control signal. The derace latch transmits the data signal from the first memory module to the latch according to the second phase of both of the first control signal and the second control signal.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: May 10, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jack Liu
  • Patent number: 9336881
    Abstract: A variable resistance nonvolatile memory device includes: a nonvolatile memory element; an NMOS transistor connected to the nonvolatile memory element; a source line connected to the NMOS transistor; a bit line connected to the nonvolatile memory element. When a control circuit causes the nonvolatile memory element to be in the low resistance state, the control circuit controls to flow a first current from a first voltage source to a reference potential point, and applies a first gate voltage to a gate of a NMOS transistor, and when the control circuit causes the nonvolatile memory element to be in the high resistance state, the control circuit controls to flow a second current from a second voltage source to the reference potential point, and applies a second gate voltage to the gate of the NMOS transistor, the second gate voltage being lower than the first gate voltage.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: May 10, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Kazuhiko Shimakawa, Ryotaro Azuma, Ken Kawai, Shunsaku Muraoka
  • Patent number: 9336866
    Abstract: A write method of a storage device includes determining whether to perform a coarse program operation based on information about memory cells of a memory device, in response to a determination that the coarse program operation is to be performed, programming data in the memory device by performing the coarse program operation and a fine program operation, and in response to a determination that the coarse program operation is not to be performed, programming data in the memory device by performing the fine program operation.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: May 10, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: DongHun Kwak, Dongkyo Shim, Kitae Park, Hyun-Wook Park
  • Patent number: 9330773
    Abstract: A semiconductor memory device according to an embodiment of the present invention includes a first cell string and a second cell string coupled to a first word line group and a second word line group, respectively. An operating method of the semiconductor memory device may include forming a channel in the second cell string by applying a pass voltage to the second word line group, reflecting data of a selected memory cell coupled to a selected word line of the first word line group, among memory cells of the first cell string, on the channel of the second cell string through the bit line, and determining the data of the selected memory cell by sensing a quantity of electric charge of the second cell string through the bit line.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: May 3, 2016
    Assignee: SK Hynix Inc.
    Inventors: In Geun Lim, Min Kyu Lee
  • Patent number: 9312019
    Abstract: According to an embodiment, an operation method for a memory device which has a first memory element and a second memory element respectively provided on both sides of a semiconductor member includes applying a first voltage to a second word line, the first voltage being negative for a voltage of a cell source line, and applying a second voltage to a first word line, the second voltage being positive for the voltage of the cell source line when reading out a data from the first memory element.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: April 12, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Wataru Sakamoto