Abstract: An operator control unit for operator control of a cooktop comprising at least two cooking zones, with at least one of the cooking zones having two heating rings that can be separately activated. The operator control unit comprises at least one selection element to select a cooking zone, at least one adjusting element, it being possible to adjust a heating power of a selected cooking zone by operating said adjusting element, and a control unit coupled to the at least one selection element and the at least one adjusting element, and which detects operation of the at least one selection element and the at least one adjusting element. The control unit can control at least one of the at least two heating rings of the selected cooking zone in the event of an operating duration in a second time period which differs from the first time period range.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array in which a plurality of nonvolatile memory cells are arrayed, and a program voltage generator that switches current supply amount based on the number of memory cells that are programmed at the same time, among the plurality of memory cells. The nonvolatile semiconductor memory device further includes a selection circuit that selects, among the plurality of memory cells, one or more memory cells that are programmed, to flow a current outputted by the program voltage generator.

Abstract: An apparatus, system, and method are disclosed to manage solid-state storage media by determining one or more configuration parameters for the solid-state storage media. A media characteristic module references one or more storage media characteristics for a set of storage cells of solid-state storage media. A configuration parameter module determines a configuration parameter for the set of storage cells based on the one or more storage media characteristics. A storage cell configuration module configures the set of storage cells to use the determined configuration parameter.

Abstract: An electrically addressed non-volatile memory is maintained by measuring a voltage threshold for each selected memory cell in the electrically addressed non-volatile memory. The voltage threshold is a voltage around which a controllable voltage signal applied to a control gate of a selected memory cell produces a change in value read from the selected memory cell. A measured voltage threshold distribution of the measured voltage thresholds is generated for the selected memory cells. The voltage threshold distribution is analyzed to identify memory cells having greater probabilities of read errors, for example. In response to the analysis, an operating parameter that affects the memory cells identified as having greater probabilities of read errors is selectively changed.

Abstract: A semiconductor apparatus has a plurality of chips stacked therein. Read control signals for controlling read operations of the plurality of chips are synchronized with a reference clock such that the time taken from the application of a read command to the output of data for each of the plurality of chips is maintained substantially the same.

Abstract: A block decoder of a semiconductor memory device includes a control signal generation circuit configured to generate an initial control signal and a block selection control signal in response to memory block selection addresses, an output node control circuit configured to set up an initial voltage of an output node in response to the initial control signal, and a block selection signal generation circuit configured to generate a block selection signal by raising a potential of the output node in response to the block selection control signal and the initial voltage of the output node.

Abstract: A water heater comprises a body defining a chamber for holding water to be heated, an inlet opening and an outlet opening in communication with the chamber for flowing water therethrough and one or more power consuming features/functions including a heater for heating the water within the chamber. A controller is operatively connected to the one or more power consuming features/functions. The controller is configured to receive and process a signal indicative of a utility state. The controller operates the water heater in one of a plurality of operating modes, including at least a normal operating mode and an energy savings mode, in response to the received signal. The controller is configured to at least one of selectively adjust and deactivate at least one of the one or more power consuming features/functions to reduce power consumption of the water heater in the energy savings mode.

Abstract: A magnetic memory includes a magnetization recording layer, a first terminal, a second terminal, a magnetization pinned layer and a non-magnetic layer. The magnetization recording layer has a vertical magnetic anisotropy and includes a ferromagnetic layer. The first terminal is connected to one end of a first region in the magnetization recording layer. The second terminal is connected to the other end of the first region. The non-magnetic layer is arranged on the first region. The magnetization pinned layer is arranged on the non-magnetic layer and is located on the side opposite to the first region. The magnetization recording layer includes: a first extension portion located outside the first terminal in the magnetization recording layer; and a property changing structure that is arranged in the first extension portion and substantially changes a magnetization switching property of the magnetization recording layer.

Abstract: A method of writing to magnetic tunnel junctions (MTJs) of a magnetic memory array includes storing in-coming data in a cache register, reading the present logic state of a first one of a set of at least two MTJs, the set of at least two MTJs including the first MTJ and a second MTJ. The in-coming data is to be written into the second MTJ. Further steps are storing the read logic state into a data register, swapping the contents of the data register and the cache register so that the cache register stores the read logic state and the data register stores the in-coming data, applying a first predetermined voltage level to the set of MTJs thereby causing the first MTJ to be over-written, applying a second predetermined voltage level to the set of MTJs, and storing the in-coming data into the second MTJ.

Abstract: A delay locked loop includes a closed loop circuit configured to generate preliminary delay information, a control unit configured to update the preliminary delay information into delay information in response to a control signal, and a first delay unit configured to delay an input clock signal by a first delay value determined by the delay information and generate an output clock signal.

Abstract: A method of suppressing propagation of leakage current in an array of switching devices. The method includes providing a dielectric breakdown element integrally and serially connected to a switching element within each of the switching device. A read voltage (for example) is applied to a selected cell. The propagation of leakage current is suppressed by each of the dielectric breakdown element in unselected cells in the array. The read voltage is sufficient to cause breakdown in the selected cells but insufficient to cause breakdown in the serially connected, unselected cells in a specific embodiment. Methods to fabricate of such devices and to program, to erase and to read the device are provided.

Abstract: Methods and systems for addressing threshold voltage shifts of memory cells. A method includes reading a pattern of data from a first plurality of memory cells, comparing the read of the pattern of data with a known pattern of data using a reference, and if the read of the pattern of data and the known pattern of data do not match, adjusting the reference to find a reference level that results in a matching of a read of the pattern of data and the known pattern of data. Thereafter, trim sector data is read into a second plurality of memory cells using the adjusted reference level.

Abstract: In a method of operating a nonvolatile memory device, at least one among memory cell blocks of the nonvolatile memory device is designated as a content addressable memory (CAM) block which includes a plurality of CAM cells coupled to respective word lines of the nonvolatile memory device. Chip information for operations of the nonvolatile memory device is stored in the CAM cells which are coupled to a selected word line, whereas the remaining CAM cells of the CAM block are in an erased state.

Abstract: A semiconductor memory includes: a non-volatile memory cell including a floating gate and a memory transistor; a state machine that generates a normal program signal for performing a normal program operation and a verify signal for performing a verify operation and generates a soft program signal for performing a soft program operation when detecting a fail in the verify operation after the normal program operation, whether a threshold voltage of the memory transistor reaches a value being checked in the verify operation; a voltage generating circuit that generates a normal program voltage and a verify voltage based on the normal program signal and the verify signal and generates a soft program voltage based on the soft program signal; and a determination circuit that detects a pass when the threshold voltage reaches the value and detects the fail when the threshold voltage does not reach the value.

Abstract: A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic.

Abstract: A memory includes a capacitor coupled to a write bit line or a word line. An initializer is configured to initialize a voltage level at a first node between the capacitor and the write bit line or a word line. An initial level adjuster is configured to adjust a voltage level of a second node at one terminal of the capacitor. A pulse generator configured to supply a pulse to the initial level adjuster to control the initial level adjuster. A boost signal is configured to be supplied to a third node on the other terminal of the capacitor opposite the first node to boost a voltage level of the write bit line lower than ground or to boost a voltage level of the word line higher than a power supply voltage.

Abstract: Embodiments of a pendant associated with a multi-process welding power supply that allows a user to switch processes and reverse an output polarity while located remotely from a power supply unit are provided. Certain embodiments include a pendant with a wire spool and wire feeder drive circuitry that is configured to activate spooling during MIG welding. Control circuitry that may include processing circuitry and memory is provided. The control system may disable redundant controls on the power supply unit user interface when the power supply unit is connected to the pendant via a supply cable. Additionally, the control system may set the process, set the polarity, enable or disable a wire feed, and enable or disable gas flow according to inputs received via a user interface on either the power supply unit or the pendant.

Abstract: Read and write operations of a non-volatile memory (NVM) bitcell have different optimum parameters resulting in a conflict during design of the NVM bitcell. A single bitline in the NVM bitcell prevents optimum read performance. Read performance may be improved by splitting the read path and the write path in a NVM bitcell between two bitlines. A read bitline of the NVM bitcell has a low capacitance for improved read operation speed and decreased power consumption. A write bitline of the NVM bitcell has a low resistance to handle large currents present during write operations. A memory element of the NVM bitcell may be a fuse, anti-fuse, eFUSE, or magnetic tunnel junction. Read performance may be further enhanced with differential sensing read operations.

Abstract: First main bit lines correspond to at least one first memory cell. Second main bit lines correspond to at least one second memory cell. At least one sense amplifier outputs read data according to a difference between a voltage of any one of the first main bit lines and a voltage of any one of the second main bit lines. A voltage supply switching section supplies a predetermined reference voltage to one of the first main bit lines corresponding to one of the second main bit lines in which a current according to a threshold voltage of the at least one second memory cell is generated. A resistance switching section forms electrical connection between a ground node and the one of the second main bit lines in which the current according to the threshold voltage of the at least one second memory cell is generated with a predetermined resistance value.

Abstract: An article of composite material includes a plurality of plies of material consolidated through the application of pressure and heating, in which each material ply is made by a resin matrix reinforced with fiber material. The article includes heating electrical resistance and temperature sensing devices embedded in the composite material, which are respectively placed in at least one interface zone between the material plies and are suitable to allow a temperature control of the article in service.