Patents Examined by Trong Phan
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Patent number: 8503260Abstract: A method of testing a semiconductor memory device comprises receiving a clock, addresses, commands, and data from a test device through channels, generating an internal bank address in response to the addresses and the commands, performing a multi-bit parallel test for each of a plurality of banks based on the addresses, the commands, the data, and the internal bank address, and providing the test device with a test result signal.Type: GrantFiled: May 10, 2011Date of Patent: August 6, 2013Assignee: Hynix Semiconductor Inc.Inventors: Jeong-Tae Hwang, Jeong-Hun Lee
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Patent number: 8503235Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.Type: GrantFiled: November 17, 2011Date of Patent: August 6, 2013Assignee: Solid State Storage Solutions, Inc.Inventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi Inoue, Shigemasa Shiota, Masashi Naito
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Patent number: 8503211Abstract: A configurable memory subsystem includes a memory module with a circuit board having a first and a second memory-containing device (MCD) pair mounted thereto. Each MCD pair has a first MCD in communication with a second MCD. Each MCD has an input port, an output port, and a memory each communicating with a bridge. In response to a command, the bridge transfers at least one of a portion of a data packet from the input port to the output port or to the memory, or transfers a portion of a memory packet from the memory to the output port. A loop-back device receives the command and the data packet form the first MCD pair and transmits the command and data packet to the second MCD pair.Type: GrantFiled: April 29, 2010Date of Patent: August 6, 2013Assignee: MOSAID Technologies IncorporatedInventors: Peter Gillingham, Roland Schuetz
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Patent number: 8495275Abstract: A list structure control circuit includes memories each individually stores data, selection circuits arranged for each of the memories and series-connect the memories so that data stored in each memory has an order relation, and an update control circuit that adds a position selection signal which specifies a position for data insertion or data removal to a fixed value, or subtracts the position selection signal from the fixed value, generates an enable signal based on the calculation result, and controls data retention performed in the memories or data update performed in the memories using data of a memory in precedent stages based on the generated enable signal, wherein the selection circuits are controlled based on the position selection signal at the time of the data insertion, and data stored in a memory located at the position specified by the position specification signal is updated with data to be inserted.Type: GrantFiled: December 29, 2010Date of Patent: July 23, 2013Assignee: Fujitsu LimitedInventor: Takashi Toyoshima
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Patent number: 8482959Abstract: A method of repairing a memory device is provided. If an erase process is unsuccessful, a repair process is performed. A programmed state of the memory device is determined, A subsequent erase process dependent on the programmed state is performed. Also, a method of programming and erasing a memory device is provided. The memory device includes first and second electrodes and a switching layer therebetween. A first on-state resistance characteristic of the memory device is provided in programming the memory device by application of a first voltage to the gate of a transistor in series with the memory device. Other on-state resistance characteristics of the memory device, different from the first on-state resistance characteristic, may be provided by application of other voltages, different from the first voltage, to the gate of the transistor.Type: GrantFiled: December 13, 2011Date of Patent: July 9, 2013Assignee: Spansion LLCInventors: Swaroop Kaza, Sameer Haddad
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Patent number: 8482968Abstract: An example embodiment is an apparatus for controlling a magnetic direction of a magnetic free layer. The apparatus includes a writer with a first magnetic write layer and a second magnetic write layer. Applying a write voltage across first and second magnetic write layers causes a magnetic anisotropy of one of the magnetic write layers to switch from parallel to the plane of the magnetic write layers to orthogonal to the plane of the magnetic write layers. The magnetic write layer with the magnetic anisotropy parallel to the plane of the magnetic write layers induces the magnetic direction in the magnetic free layer.Type: GrantFiled: November 13, 2010Date of Patent: July 9, 2013Assignee: International Business Machines CorporationInventor: Daniel C. Worledge
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Patent number: 8482967Abstract: An apparatus and method for enhancing data writing and retention to a magnetic memory element, such as in a non-volatile data storage array. In accordance with various embodiments, a programmable memory element has a reference layer and a storage layer. The reference layer is provided with a fixed magnetic orientation. The storage layer is programmed to have a first region with a magnetic orientation antiparallel to said fixed magnetic orientation, and a second region with a magnetic orientation parallel to said fixed magnetic orientation. A thermal assist layer may be incorporated into the memory element to enhance localized heating of the storage layer to aid in the transition of the first region from parallel to antiparallel magnetic orientation during a write operation.Type: GrantFiled: November 3, 2010Date of Patent: July 9, 2013Assignee: Seagate Technology LLCInventors: Haiwen Xi, Yuankai Zheng, Xiaobin Wang, Dimitar V. Dimitrov, Pat J. Ryan
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Patent number: 8477558Abstract: Low supply voltage memory apparatuses are presented. In one embodiment, a memory apparatus comprises a memory and a memory controller. The memory controller includes a read controller. The read controller prevents a read operation to a memory location from being completed, for at least N clock cycles after a write operation to the memory location, where N is the number of clock cycles for the memory location to stabilize after the write operation.Type: GrantFiled: October 30, 2008Date of Patent: July 2, 2013Assignee: Intel CorporationInventors: Jaume Abella, Xavier Vera, Javier Carretero Casado, Pedro Chaparro Monferrer, Antonio González
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Patent number: 8477521Abstract: A fuse circuit includes a plurality of fuse cells, an amplification unit, and a plurality of registers. The amplification unit is configured to sequentially amplify data stored in the fuse cells. The registers are configured to sequentially store data amplified by the amplification unit.Type: GrantFiled: December 29, 2010Date of Patent: July 2, 2013Assignee: Hynix Semiconductor Inc.Inventors: Kwi-Dong Kim, Jun-Gi Choi
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Patent number: 8472265Abstract: A novelty repairing method and circuit are provided by the embodiments of the present invention, wherein the input/output (IO) compression manner can be used therein to reduce the access time during the chip probing 1 (CP1) test, and each redundant column selected line (RCSL) can be divided into several partial redundant column selected lines (P-RCSLs) which are respectively responsible for repairing the defects of the corresponding regions. Based upon the repairing method, the memory circuit can reduce the number of the RCSLs. Furthermore, a variable region dividing manner is applied therein, so as to increase the probability for repairing the defect of the memory circuit.Type: GrantFiled: May 10, 2011Date of Patent: June 25, 2013Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Jen-Shou Hsu
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Patent number: 8472230Abstract: A selective access memory circuit (SAMC) is described. The SAMC is a class of complex programmable memory device (CPMD) that reconfigures access to memory cells by using gates in an integrated gate array mechanism configured at regular intervals in memory arrays. CPMDs are applied to embedded controllers, microprocessors, DSPs and system on chip (SoC) circuit architectures.Type: GrantFiled: February 16, 2011Date of Patent: June 25, 2013Inventor: Neal Solomon
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Patent number: 8467217Abstract: The semiconductor device comprises first and second memory cells, first and second bit lines connected to the first/second memory cells, first and second amplifiers connected to the second bit line, a local input/output line commonly connected to the first/second amplifiers, first and second local column switches connected between the first/second amplifiers and the local input/output line, a second local column switch connected between the second amplifier and the local input/output line, a column select line, a first global column switch connected between the column select line and the first local column switch and controlling a connection therebetween in response to a first select signal, and a second global column switch connected between the column select line and the second local column switch and controlling a connection therebetween in response to a first select signal.Type: GrantFiled: February 23, 2011Date of Patent: June 18, 2013Assignee: Elpida Memory, Inc.Inventors: Shinichi Takayama, Kazuhiko Kajigaya, Akira Kotabe, Satoru Akiyama, Tomonori Sekiguchi
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Patent number: 8461483Abstract: An engine driven welding system includes two power generators, each having a rotor and a stator. Each rotor is mounted on a respective drive shaft, with one of the drive shafts being driven by the engine and the other drive shaft being releasably coupled to the engine driven drive shaft. This provides a modular type construction of the welding system, in that the outboard power generator can be selected or changed as needed for a particular application. The coupled drive shafts are supported by two bearing assemblies. Also disclosed as additional features for any welding system power supply is a removable plate having one or more connectors releasably attached thereto for facilitating installation of an electrical component for a welding system power supply; and also a power switch having a member that restricts rotational movement of the switch.Type: GrantFiled: July 22, 2010Date of Patent: June 11, 2013Assignee: Lincoln Global, Inc.Inventors: Samir F. Farah, David Joseph Bender, Edward A. Enyedy, Carmen J. Delisio
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Patent number: 8462536Abstract: The present description relates to non-volatile memory arrays and the operation thereof In at least one embodiment, the non-volatile memory array may include a plurality of memory modules coupled in a daisy chain with enable in/out signals, and a single chip enable signal coupled in parallel to each memory module. With such a configuration, all memory units within each of the memory modules of each memory array may be addressed with the single chip enable signal.Type: GrantFiled: March 11, 2011Date of Patent: June 11, 2013Assignee: Intel CorporationInventors: Dean Nobunaga, Terry Grunzke, Ali Ghalam
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Patent number: 8462561Abstract: A burst read control circuit acts as an interface to allow a burst-read capable device to execute burst reads from a page-mode capable memory device. The burst read control circuit coordinates burst read requests from the burst-read capable device and subsequent responses from the page-mode capable memory device by accessing subsequent and contiguous memory locations of the page-mode capable memory device.Type: GrantFiled: August 3, 2011Date of Patent: June 11, 2013Assignee: Hamilton Sundstrand CorporationInventor: Dean Anthony Rametta
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Patent number: 8462549Abstract: Methods and apparatus are provided for read-side intercell interference mitigation in flash memories. A flash memory device is read by obtaining a read value for at least one target cell; obtaining a value representing a voltage stored in at least one aggressor cell that was programmed after the target cell; determining intercell interference for the target cell from the at least one aggressor cell; and obtaining a new read value that compensates for the intercell interference by removing the determined intercell interference from the read value for the at least one target cell. The new read value can optionally be provided to a decoder. In an iterative implementation, one or more intercell interference mitigation parameters can be adjusted if a decoding error occurs.Type: GrantFiled: June 30, 2009Date of Patent: June 11, 2013Assignee: LSI CorporationInventors: Erich F. Haratsch, Milos Ivkovic, Victor Krachkovsky, Nenad Miladinovic, Andrei Vityaev, Johnson Yen
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Patent number: 8456895Abstract: A mechanism is provided for bidirectional writing. A structure includes a reference layer on top of a tunnel barrier, a free layer underneath the tunnel barrier, a metal spacer underneath the free layer, an insulating magnet underneath the metal spacer, and a high resistance layer underneath the insulating layer. The high resistance layer acts as a heater in which the heater heats the insulating magnet to generate spin polarized electrons. A magnetization of the free layer is destabilized by the spin polarized electrons generated from the insulating magnet. A voltage is applied to change the magnetization of the free layer when the magnetization is destabilized. A polarity of the voltage determines when the magnetization of the free layer is parallel and antiparallel to a magnetization of the reference layer.Type: GrantFiled: May 3, 2011Date of Patent: June 4, 2013Assignee: International Business Machines CorporationInventors: David W. Abraham, Niladri N. Mojumder, Daniel C. Worledge
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Patent number: 8456894Abstract: A mechanism is provided for noncontact writing. Multiple magnetic islands are provided on a nonmagnetic layer. A reference layer is provided under the nonmagnetic layer. A spin-current is caused to write a state to a magnetic island of the multiple magnetic islands by moving a heat source to heat the magnetic island.Type: GrantFiled: May 3, 2011Date of Patent: June 4, 2013Assignee: International Business Machines CorporationInventors: David W. Abraham, Jonathan Z. Sun, Guohan Hu
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Patent number: 8456926Abstract: Memory circuit includes; an array, row decoder, column decoder, addressing circuit to receive an address of the data bit, control logic receiving commands and transmitting control signals to memory system blocks, and sensing and write driver circuits coupled to a selected column. A hidden read compare circuit couples between the sensing circuit and write driver, which couples an error flag to the control logic circuit responsive to a comparison between a data bit in the input latch and a data-out read from the memory array. A write error address tag memory is responsive to the error flag and is coupled to the addressing circuit via a bidirectional bus. A data input output circuit having first and second bidirectional buses to transmit and receive said data bit is provided. Write error address tag memory stores the address if the error flag is set and provides the address during a re-write operation.Type: GrantFiled: January 25, 2011Date of Patent: June 4, 2013Assignee: Grandis, Inc.Inventors: Adrian E. Ong, Vladimir Nitikin
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Patent number: 8446755Abstract: A memory system that reduces the memory cycle time of a memory cell by performing an incomplete write operation. The voltage on a storage node of the memory cell does not reach a full supply voltage during the incomplete write operation. The incomplete write operation is subsequently completed by one or more additional accesses, wherein the voltage on the storage node is pulled to a full supply voltage. The incomplete write operation may be completed by: subsequently writing the same data to the memory cell during an idle cycle; subsequently writing data to other memory cells in the same row as the memory cell; subsequently reading data from the row that includes the memory cell; or refreshing the row that includes the memory cell during an idle cycle. One or more idle cycles may be forced to cause the incomplete write operation to be completed in a timely manner.Type: GrantFiled: February 8, 2012Date of Patent: May 21, 2013Assignee: MoSys, Inc.Inventor: Richard S. Roy