Abstract: A method of selecting a reference circuit for a write operation is disclosed. The method comprises selecting a reference circuit for a write operation based on an output of a row decode circuit and a column decode circuit. The reference circuit is programmed concurrently with a write operation of at least one of a plurality of memory cells in a memory array without requiring an external reference circuit write command.

Abstract: A semiconductor device includes a semiconductor substrate having first and second edge lines, address pads along the first edge line, and memory mats, each including normal memory blocks and a spare memory block. Each normal memory block has nonvolatile memory cells and is a unit of batch erase. The memory mats are arranged in a U-shaped area having a hollow portion facing the second edge line. The device includes column decoders arranged correspondingly to the memory mats, an analog/logic circuit arranged in the hollow portion, and a power supply pad arranged between the analog/logic circuit and the second edge line. The analog/logic circuit includes a charge pump circuit. The device further includes a first power supply interconnection supplying power supply voltage to the charge pump circuit from the power supply pad, and a second power supply interconnection supplying power supply voltage to the column decoder from the power supply pad.

Abstract: A control voltage generation circuit for generating a control voltage for controlling a high-voltage transistor includes an input node configured to receive a first enable signal; an output node configured to generate the control voltage, a transferor configured to transfer a voltage of the input node to the output node in response to a transfer signal, an enabling voltage driver configured to drive the output node with a high voltage when the first enable signal is enabled, and a disabling voltage driver configured to drive the output node with a negative voltage when a second enable signal is enabled in a negative mode.

Abstract: The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted, each of search line drivers transfers search data to each CAM cell of a CAM memory array via a search line pair. The search line enable signal is transmitted to the search line drivers via a single control signal line coupled to the search control circuit. The control signal line is coupled to the search line drivers in such a manner that the search line enable signal passes through coupling nodes between the search line drivers and the control signal line in an arrangement order of the search line drivers from the side far away as viewed from match amplifiers.

Abstract: A memory arrangement is provided having a plurality of memory elements, the elements being associated with a memory space that can be addressed in a row and column fashion during a write or a read access. The memory arrangement further includes a first macro bank comprising a first plurality of memory cells comprising a first subset of the memory elements and a second macro bank comprising a second plurality of memory cells comprising a second subset of the memory elements. The memory arrangement further includes an address resolution stage for addressing the memory cells in the respective macro banks. The memory cells are arranged so that the memory space is partitioned into a plurality of non-overlapping basic matrices, whereby each basic matrix is mapped to a given macro bank and wherein the memory cells are arranged logically so that the memory space is partitioned into a plurality of non-overlapping logic matrices of a given size, each logic matrix being of a size equal or larger than a basic matrix.

Abstract: Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged in a stack. The identification circuit can determine an identification of its respective memory die responsive to how, if coupled, the identification circuit is coupled to the external select connection node.

Abstract: A nonvolatile memory device includes a memory cell array having multiple memory cells, a data input/output buffer for temporarily storing data to be stored in the memory cells, and a data scanner for scanning the data stored temporarily in the data input/output buffer. The nonvolatile memory device further includes control logic for reading address information of a memory cell in which at least a portion of the data is to be stored and selectively performing a data scan operation according to the read address information.

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

Abstract: A nonvolatile memory device and a programming method thereof perform a programming verification step including a selective verification step and a sequential verification step. In the selective verification step, a data input/output (I/O) circuit selectively precharges a selected bit line according to a temporary programmed state of stored data. In the sequential verification step, the data I/O circuit selectively precharges each bit line according to the result of the previous selective verification step or a previous sequential verification step. According to the programming method, because a memory cell not requiring a programming verification step is not precharged in the programming verification step, an ON cell current does not flow therethrough. Accordingly, the current flowing through a common source line during verification can be reduced.

Abstract: A method of operating a semiconductor memory device includes applying a program pass voltage to unselected word lines, applying a program voltage of a third level to a selected word line in order to raise threshold voltages of third memory cells, decreasing a level of the program voltage from the third level to a second level and discharging channel regions of second cell strings including second memory cells in order to raise threshold voltages of second memory cells, and decreasing a level of the program voltage from the second level to a first level and discharging channel regions of first cell strings including first memory cells in order to raise threshold voltages of first memory cells. The cell strings are disconnected from a bit line while a voltage level of the unselected word lines rises to a level of the program pass voltage.

Abstract: Circuits for a memory array and a method of operating a configurable memory block are disclosed. An embodiment of the disclosed memory circuits includes a first memory block coupled to a second memory block to form an array of memory blocks. Each of the memory blocks has multiple bit lines with a dedicated address decoder coupled to the bit lines from each of the memory blocks. Switches are placed in between the first and second memory blocks such that each of the bit lines from the first memory block is connected to a corresponding bitline from the second memory block through one of the switches. The switches may be used to either connect the second memory block to the first memory block or disconnect the second memory block from the first memory block.

Abstract: According to one embodiment, a semiconductor device includes a first circuit unit having first and second interconnects, a second circuit unit having third and fourth interconnects, and an intermediate unit provided therebetween and having first and second transistors juxtaposed to each other along a direction perpendicular to a direction from the first circuit unit toward the second circuit unit. A high impurity concentration region in a first connection region of one diffusion layer of the first transistor is connected to the first interconnect, and other diffusion layer is connected to the third interconnect. A distance from the first connection region to a gate is longer than a distance from the second connection region to a gate. An midpoint region with a narrower width than the first connection region is provided between the gate and the first connection region of the one diffusion layer of the first transistor.

Abstract: A sensing circuit (100) for sensing the content of a memory cell (101), wherein the sensing circuit comprises a sense node (103) connectable to the memory cell (101) so that a signal indicative of the content of the memory cell (101) is providable to the sense node (103). The sensing circuit (100) further comprises a logic gate (102) having a first input, a second input and an output, wherein a reference signal (105) is providable to the first input and wherein the sense node (103) is coupled to the second input. The sensing circuit (100) further comprises a feedback loop (104) for coupling the output of the logic gate (102) to the second input of the logic gate (102) so that, during sensing the content of the memory cell (101), an electrical potential at the sense node (103) is used to make a decision but after a result is obtained, the memory and sense amplifier combination are configured so that the result is held indefinitely and so that no static current continues to flow.

Abstract: A semiconductor device according to the present invention includes plural controlled chips CC0 to CC7 that hold mutually different layer information, and a control chip IF that supplies in common layer address signals A13 to A15 and a command signal ICMD to the controlled chips. Each bit that constitutes the layer address signals A13 to A15 is transmitted via at least two through silicon vias that are connected in parallel for each controlled chip out of plural first through silicon vias. Each bit that constitutes the command signal ICMD is transmitted via one corresponding through silicon via that is selected by an output switching circuit and an input switching circuit. With this configuration, the layer address signals A13 to A15 reach the controlled chips earlier than the command signal ICMD.

Abstract: A method of making a NAND string includes forming a semiconductor layer over a major surface of a substrate, patterning the semiconductor layer into an elongated nanowire shaped channel extending substantially parallel to the major surface of the substrate, forming a tunneling dielectric layer over the channel, forming a plurality of charge storage regions over the tunneling dielectric layer and undercutting the channel using the plurality of charge storage regions as mask. The channel has a narrower width than each charge storage region width, and an overhanging portion of each of the plurality of charge storage regions overhangs the channel. The method also includes forming a blocking dielectric layer over the plurality of charge storage regions, such that the blocking dielectric layer fills a space below the overhanging portion of each of the plurality of charge storage regions and forming a plurality of control gates over the blocking dielectric layer.

Abstract: In a non-volatile storage system, during a verify operation, a verify voltage of a currently-sensed target data state is applied to a selected word line. A higher, nominal bit line voltage is used for the storage elements which have the currently-sensed target data state and a verify status of pass or no pass, a target data state lower than the currently-sensed target data state and a verify status of pass or no pass, or a target data state higher than the currently-sensed target data state and a verify status of pass. A lower bit line voltage is used for the storage elements which have the target data state higher than the currently-sensed target data state and a verify status of no pass, to enhance channel-to-channel coupling, as an offset to floating gate-to-floating gate coupling which is later caused by these storage elements.

Abstract: Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, such as PROM, OTPROM, and other such programmable non-volatile memories. The circuitry employs an antifuse scheme that includes an array of memory bitcells, each containing a program device and an antifuse element configured with current path isolation well and for storing the memory cell state. The bitcell configuration, which can be used in conjunction with column/row select circuitry, power selector circuitry, and/or readout circuitry, allows for high-density memory array circuit designs and layouts.

Abstract: A connector for connecting a welding torch, where the connector body and the house are made of insulating material and designed as a unit in one piece connected by a rear wall. The connector includes an insert made of electrically conductive material carrying a threaded surface made of electrically conductive material and a contact surface. The insert can be fitted in a nest formed by a side surface of the connector body part and a surface of the house part opposite to the side surface. An opening on the sidewall of the house part provides access to the side surface of the insert for connecting the side surface to a current, and the insert is secured rotationally in the nest.

Abstract: The invention relates to a welding method for implementing and monitoring a welding process, whereby a power source (2) and a feeding device (10) for the welding rod (11) are controlled by means of a control device (4), and whereby at least one control variable is measured or calculated from characteristic variables of the arc during the welding process.

Abstract: A memory system with delay locked loop (DLL) bypass control including a method for accessing memory that includes receiving a memory read command at a memory device. The memory device is configured to operate in a DLL off-mode to bypass a DLL clock as input to generating a read clock. A DLL power-on command is received at the memory device and in response to receiving the DLL power-on command a DLL initialization process is performed at the memory device. The memory read command is serviced at the memory device operating in the DLL off-mode, the servicing overlapping in time with performing the DLL initialization process. The memory device is configured to operate in a DLL on-mode to utilize the DLL clock as input to generating the read clock in response to a specified period of time elapsing. The specified period of time is relative to receiving the DLL power-on command.