Patents Examined by Trung Dang
  • Patent number: 8304284
    Abstract: In some aspects, a method of fabricating a memory cell is provided that includes fabricating a steering element above a substrate, and fabricating a reversible-resistance switching element coupled to the steering element by fabricating a carbon nano-tube (“CNT”) seeding layer by depositing a silicon-germanium layer above the substrate, patterning and etching the CNT seeding layer, and selectively fabricating CNT material on the CNT seeding layer. Numerous other aspects are provided.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: November 6, 2012
    Assignee: SanDisk 3D LLC
    Inventor: April D. Schricker
  • Patent number: 8264052
    Abstract: A symmetric Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell and STT-MRAM bit cell array are disclosed. The STT-MRAM bit cell includes a poly silicon layer, a magnetic tunnel junction (MTJ) storage element, and a bottom electrode (BE) plate. The storage element and bottom electrode (BE) plate are symmetric along a center line of the poly silicon layer.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: September 11, 2012
    Assignee: QUALCOMM Incorporated
    Inventor: William Xia
  • Patent number: 8053847
    Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing carbon, boron, and hydrogen into the semiconductor substrate at two sides of the spacer for forming a doped region. The molecular weight of the molecular cluster is preferably greater than 100. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the doped region.
    Type: Grant
    Filed: November 28, 2008
    Date of Patent: November 8, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Tsai-Fu Hsiao, Ching-I Li, Po-Yuan Chen, Chun-An Lin, Hsiang-Ying Wang, Chao-Chun Chen, Chin-Cheng Chien
  • Patent number: 8012854
    Abstract: It is an object of the present invention to provide a peeling method that causes no damage to a layer to be peeled and to allow not only a layer to be peeled with a small surface area but also a layer to be peeled with a large surface area to be peeled entirely. Further, it is also an object of the present invention to bond a layer to be peeled to various base materials to provide a lighter semiconductor device and a manufacturing method thereof. Particularly, it is an object to bond various elements typified by a TFT, (a thin film diode, a photoelectric conversion element comprising a PIN junction of silicon, or a silicon resistance element) to a flexible film to provide a lighter semiconductor device and a manufacturing method thereof.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: September 6, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Junya Maruyama, Yumiko Ohno
  • Patent number: 8013402
    Abstract: Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: September 6, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ha-Jin Lim, Jong-Ho Lee, Hyung-Suk Jung
  • Patent number: 8008710
    Abstract: A memory string has a semiconductor layer with a joining portion that is formed to join a plurality of columnar portions extending in a vertical direction with respect to a substrate and lower ends of the plurality of columnar portions. First conductive layers are formed in a laminated fashion to surround side surfaces of the columnar portions and an electric charge storage layer, and function as control electrodes of memory cells. A second conductive layer is formed around the plurality of columnar portions via a gate insulation film, and functions as control electrodes of selection transistors. Bit lines are formed to be connected to the plurality of columnar portions, respectively, with a second direction orthogonal to a first direction taken as a longitudinal direction.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: August 30, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi
  • Patent number: 7994631
    Abstract: A substrate for an integrated circuit package is disclosed. The substrate comprises a core comprising a first dielectric layer having a first thickness; conductive traces formed on the first dielectric layer for routing signals within the integrated circuit package, wherein the conductive traces have a second thickness; and a substrate support structure comprising conductive traces formed on the first dielectric layer, where the conductive traces of the substrate support structure have a third thickness which is greater than the second thickness. A method of forming an integrated circuit package is also disclosed.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: August 9, 2011
    Assignee: Xilinx, Inc.
    Inventor: Leilei Zhang
  • Patent number: 7989916
    Abstract: An article includes a top electrode that is embedded in a solder mask. An article includes a top electrode that is on a core structure. A process of forming the top electrode includes reducing the solder mask thickness and forming the top electrode on the reduced-thickness solder mask. A process of forming the top electrode includes forming the top electrode over a high-K dielectric that is in a patterned portion of the core structure.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: August 2, 2011
    Assignee: Intel Corporation
    Inventors: John J. Tang, Xiang Yin Zeng, Jiangqi He, Ding Hai
  • Patent number: 7989866
    Abstract: DRAM cell arrays having a cell area of about 4 F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: August 2, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Todd R. Abbott, Homer M. Manning
  • Patent number: 7989804
    Abstract: A test pattern structure including a first conductive layer and a second conductive layer is provided. The second conductive layer is directly disposed on the first conductive layer and connected to the first conductive layer through a plurality of connection interfaces. The test pattern structure of the present invention can detect the interconnection failure quickly and correctly without SEM identification.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: August 2, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Da-Jiang Yang, Chih-Ping Lee, Rui-Huang Cheng, Xing-Hua Zhang, Xu Ma, Xiao-Fei Han, Hong Ma, Hong Liao, Yuan-Li Ding
  • Patent number: 7982207
    Abstract: A light emitting diode (LED) has an n-type semiconductor layer, an active layer, a p-type semiconductor layer, and a transparent electrode layer. The LED includes a tunnel layer interposed between the p-type semiconductor layer and the transparent electrode layer, an opening arranged in the transparent electrode layer so that the tunnel layer is exposed, a distributed Bragg reflector (DBR) arranged in the opening, and an electrode pad arranged on the transparent electrode layer to cover the DBR in the opening.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: July 19, 2011
    Assignee: Seoul Opto Device Co., Ltd.
    Inventors: Hwa Mok Kim, Dae Won Kim, Dae Sung Kal
  • Patent number: 7977697
    Abstract: The present invention provides a light emitting device which comprises a light emitting element, a mounting board on which the light emitting element is mounted, a metal-made reflector surrounding the side surfaces of the light emitting element on the mounting board, a conductor for electrically connecting the light emitting element with the mounting board, and a sealing resin fitted within the reflector to cover and seal the light emitting element and the conductor. The mounting board includes a metal-made base board, and an insulating board laminated on the base board and formed with a window hole extending therethrough which is larger than the outer periphery of the light emitting element. A mount for carrying the light emitting element thereon is disposed on the base board within the window hole with a clearance defined from side surfaces of the window hole.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: July 12, 2011
    Assignee: NEC Lighting, Ltd.
    Inventors: Yoshinori Ueji, Katsuyuki Okimura
  • Patent number: 7977754
    Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. The semiconductor device comprises a semiconductor substrate; an active region of the substrate, wherein the active region includes at least one transistor; and a passive region of the substrate, wherein the passive region includes at least one resistive structure disposed on an isolation region, the at least one resistive structure in a lower plane than the at least one transistor.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: July 12, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry Chuang, Kong-Beng Thei
  • Patent number: 7973310
    Abstract: Semiconductor package structures and methods for manufacturing the same are provided. The semiconductor package structure comprises a substrate unit and a first chip stack structure. The substrate unit comprises a circuit structure having test pads. The first chip stack structure comprises chips, and each of the chips has a plurality of through silicon plugs. The through silicon plugs of two adjacent chips are electrically connected and further electrically connected to the test pads of the substrate unit for electrical testing. Another semiconductor package structure provided by the present invention comprises a first semiconductor chip and a second semiconductor chip. Each of the semiconductor chips has test pads for electrical testing and a plurality of through silicon plugs connecting to the test pads. The second semiconductor chip is mounted on the first semiconductor chip, and a portion of the through silicon plugs of two semiconductor chips are electrically connected with each other.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: July 5, 2011
    Assignee: Chipmos Technologies Inc.
    Inventors: David Wei Wang, An-Hong Liu, Hao-Yin Tsai, Hsiang-Ming Huang, Yi-Chang Lee, Shu-Ching Ho
  • Patent number: 7973309
    Abstract: Provided is a test element group (TEG) pattern for detecting a void in a device isolation layer. The TEG pattern includes active regions which are parallel to each other and extend in a first direction, a device isolation layer that separates the active regions, a first contact that is formed across the device isolation layer and a first one of the active regions that contacts a surface of the device isolation layer, and a second contact that is formed across the device isolation layer and a second one of the active regions that contacts another surface of the device isolation layer.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: July 5, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Gyun Kim, Dong-Suk Shin, Joo-Won Lee, Ha-Jin Lim
  • Patent number: 7972935
    Abstract: When single crystal semiconductor layers are transposed from a single crystal semiconductor substrate (a bond wafer), the single crystal semiconductor substrate is etched selectively (this step is also referred to as groove processing), and a plurality of single crystal semiconductor layers, which are being divided in size of manufactured semiconductor elements, are transposed to a different substrate (a base substrate). Thus, a plurality of island-shaped single crystal semiconductor layers (SOI layers) can be formed over the base substrate. Further, etching is performed on the single crystal semiconductor layers formed over the base substrate, and the shapes of the SOI layers are controlled precisely by being processed and modified.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: July 5, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Ikuko Kawamata, Yasuyuki Arai
  • Patent number: 7968454
    Abstract: A method of forming a pattern structure includes forming a thin film pattern on a substrate, the thin film pattern including depression portions with first bottom widths, forming a protection layer on the thin film pattern by implanting ions into the thin film pattern, and etching a lower portion of the thin film pattern selectively using the protection layer as a mask to increase the first bottom widths of the depression portions into second bottom widths.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: June 28, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Imsoo Park, Kuntack Lee
  • Patent number: 7968971
    Abstract: A thin-body bipolar device includes: a semiconductor substrate, a semiconductor fin constructed over the semiconductor substrate, a first region of the semiconductor fin having a first conductivity type, the first region serving as a base of the thin-body bipolar device, and a second and third region of the semiconductor fin having a second conductivity type opposite to the first conductivity type, the second and third region being both juxtaposed with and separated by the first region, the second and third region serving as an emitter and collector of the thin-body bipolar device, respectively.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: June 28, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shine Chung, Fu-Lung Hsueh
  • Patent number: 7968875
    Abstract: An organic photosensitive optoelectronic device includes an anode, an organic photosensitive layer formed on the anode and having a donor portion and an acceptor portion, a hole blocking layer formed on the organic photosensitive layer so as for the organic photosensitive layer to be sandwiched between the anode and the hole blocking layer, and a cathode formed on the hole blocking layer so as for the hole blocking layer to be sandwiched between the cathode and the organic photosensitive layer. The highest occupied molecular orbitals (HOMO) of the hole blocking layer is at least 0.3 eV higher than that of the donor portion. Therefore, the optoelectronic device efficiently suppresses dark current so as to enhance sensitivity when applied to a detector.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: June 28, 2011
    Assignee: National Chiao Tung University
    Inventors: Hsin-Fei Meng, Sheng-Fu Hong, Hsin-Rong Tseng, En-Chen Chen, Chia-Hung Chu
  • Patent number: 7964909
    Abstract: A plurality of mesas are formed in the substrate. Each pair of mesas forms a trench. A plurality of diffusion areas are formed in the substrate. A mesa diffusion area is formed in each mesa top and a trench diffusion area is formed under each trench. A vertical, non-volatile memory cell is formed on each sidewall of the trench. Each memory cell is comprised of a fixed threshold element located vertically between a pair of non-volatile gate insulator stacks. In one embodiment, each gate insulator stack is comprised of a tunnel insulator formed over the sidewall, a deep trapping layer, and a charge blocking layer. In another embodiment, an injector silicon rich nitride layer is formed between the deep trapping layer and the charge blocking layer.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: June 21, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya