Abstract: A thin film panel includes a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, a data line, including a source electrode, and a drain electrode formed on the gate insulating layer or the semiconductor layer, and a pixel electrode connected to the drain electrode, wherein at least one of the gate line and the data line and drain electrode includes a first conductive layer made of a molybdenum Mo-niobium Nb alloy and a second conductive layer made of a copper Cu-containing metal.

Abstract: A semiconductor device includes an Nch transistor having a first gate electrode and a Pch transistor having a second gate electrode. The first gate electrode and the second gate electrode are made of materials causing stresses of different magnitudes.

Abstract: An electronics package has a wafer level chip scale package (WLCSP) die substrate containing electronic circuits. Through-silicon vias through the die substrate electrically connect the electronic circuits to the bottom surface of the die substrate. A package sensor is coupled to the die substrate for sensing an environmental parameter. A protective encapsulant layer covers the top surface of the die substrate. A sensor aperture over the package sensor provides access for the package sensor to the environmental parameter.

Abstract: A fabrication method for a high pin count chip package is provided herein. First, a lead frame is provided, wherein the lead frame has a chip carrier and a plurality of first lead pins configured around the chip carrier. A first channel is formed on the first lead pins to define a first contact portions and a second contact portion. A die mounting process, a wire bonding process, and a molding process are performed in turn, wherein the molding compound is utilized to encapsulate the chip, the wires, and the first channel. After that, a backside sawing process is performed to electrically isolate the first contact portions and the second contact portions. The present invention achieves high pin count chip package without changing the appearance and size of product and the reasonable width limitation of the lead pins.

Abstract: A light-emitting device used in a linear array of a plurality of them includes a semiconductor light-emitting element, a substrate on which the semiconductor light-emitting element is mounted, and a light-transmitting sealing resin formed on the front surface of the substrate to seal the semiconductor light-emitting element. Of each of the peripheral edge surfaces of the substrate and the sealing resin, at least one side surface that faces in the direction of the array is inclined in the array direction.

Abstract: A compliant bonding structure is disposed between a semiconductor light emitting device and a mount. When the semiconductor light emitting device is attached to the mount, for example by providing pressure, heat, and/or ultrasonic energy to the semiconductor light emitting device, the compliant bonding structure collapses to partially fill a space between the semiconductor light emitting device and the mount. In some embodiments, the compliant bonding structure is plurality of metal bumps that undergo plastic deformation during bonding. In some embodiments, the compliant bonding structure is a porous metal layer.

Abstract: A memory cell device includes a memory cell access layer, a dielectric material over the memory cell access layer, a memory material structure within the dielectric material, and a top electrode in electrical contact with the memory material structure. The memory material structure has upper and lower memory material portions and a memory material element therebetween. The lower memory material layer is in electrical contact with a bottom electrode. The lower memory material layer has an average lateral dimension. The memory material element defines an electrical property state change region therein and has a minimum lateral dimension which is substantially less than the average lateral dimension. In some examples the memory material element is a tapered structure with the electrical property state change region at the junction of the memory material element and the lower memory material layer.

Abstract: An embedded flash memory device and a method for fabricating the same which reduces the size of a memory device using logic CMOS fabricating processes and enhancing a coupling ratio of the memory device. The flash memory device includes a coupling oxide layer on an active area of a semiconductor substrate, a first control gate formed on and/or over the coupling oxide layer and a second control gate formed on and/or over and enclosing lateral sidewalls of the coupling oxide layer and the first control gate.

Abstract: A method for forming silicide in a semiconductor device includes simultaneously performing a cleaning process and an etching process to remove a silicide metal layer if an excessive delay in time lapses after forming the silicide metal layer. This may prevent the occurrence of liquid marks due to an oxidation reaction at an interface of the semiconductor substrate in contact with the silicide metal layer, thereby preventing silicide defects due to the excessive delay.

Abstract: The present invention relates to methods and arrangements for forming a low stress cavity package. Particular methods may be performed with existing packaging equipment. In one such method, a leadframe laminated with adhesive film is provided. Integrated circuit dice are connected to the leadframe by reflowing solder between bond pads on the active surface of each die and the leadframe. A viscous thermosetting material is dispensed around the periphery of the active surface of each die. The thermosetting material fills gaps between the solder joint connections and the adhesive film. As a result, the thermosetting material, solder joint connections, each integrated circuit die and the adhesive film define and seal a protective cavity between the active surface of the die and the adhesive film. Portions of each die, leads, solder joint connections and adhesive film are encapsulated with a molding material that is prevented from entering the sealed cavity.

Abstract: Embodiments relate to and image sensor. In embodiments, the image sensor may include a semiconductor substrate, a photodiode region, a gate electrode, a dummy gate, and an interlayer dielectric layer. The semiconductor substrate includes a field oxide layer. The photodiode region may be formed on the semiconductor substrate. The gate electrode may be formed on the semiconductor substrate. The dummy gate may be formed on the field oxide layer. The interlayer dielectric layer may be formed on one side of the dummy gate and includes an opening exposing the photodiode region.

Abstract: A semiconductor device includes a semiconductor substrate having an integrated circuit and at least one connection pad, and at least one external connection electrode electrically connected with the connection pad. A first sealing material is provided on the semiconductor substrate around the external connection electrode, each impurity concentration of an Na ion, a K ion, a Ca ion and Cl ion contained in the first sealing material being not greater than 10 ppm. A second sealing material is provided on at least one of a lower surface and a peripheral side surface of the semiconductor substrate, a total impurity concentration of an Na ion, a K ion, a Ca ion and a Cl ion contained in the second sealing material being not smaller than 100 ppm.

Abstract: A light emitting diode (LED) has an n-type semiconductor layer, an active layer, a p-type semiconductor layer, and a transparent electrode layer. The LED includes a tunnel layer interposed between the p-type semiconductor layer and the transparent electrode layer, an opening arranged in the transparent electrode layer so that the tunnel layer is exposed, a distributed Bragg reflector (DBR) arranged in the opening, and an electrode pad arranged on the transparent electrode layer to cover the DBR in the opening.

Abstract: A graphene-based device is formed with a trench in one or more layers of material, a graphene layer within the trench, and a device structure on the graphene layer and within the trench. Fabrication techniques includes forming a trench defined by one or more layers of material, forming a graphene layer within the trench, and forming a device structure on the graphene layer and within the trench.

Abstract: A graphene-based device is formed with a substrate having a trench therein, a device structure on the substrate and within the trench, a graphene layer over the device structure, and a protective layer over the graphene layer. Fabrication techniques include forming a trench in a substrate, forming a device structure within the trench, forming a graphene layer over the device structure, and forming a protective layer over the graphene layer.

Abstract: An embedded integrated circuit package system is provided forming a first conductive pattern on a first structure, connecting a first integrated circuit die on the first conductive pattern, forming a substrate forming encapsulation to cover the first integrated circuit die and the first conductive pattern, forming a channel in the substrate forming encapsulation, and applying a conductive material in the channel.

Abstract: A semiconductor light detecting element having a mesa structure comprises: a first semiconductor layer having n-type conductivity located on a semiconductor substrate, a light absorbing layer located on the first semiconductor layer, and a second semiconductor layer located on the light absorbing layer; a burying layer burying peripheries of the light absorbing layer and the second semiconductor layer. The burying layer has a band gap larger than the band gap of the light absorbing layer. The second semiconductor layer has a first region having p-type conductivity, and a second region having i-type or n-type conductivity and located between the first region and the burying layer.

Abstract: A method of manufacturing semiconductor laser device capable of reducing ?L, with manufacturing restrictions satisfied, is provided. In a distributed-feedback or distributed-reflective semiconductor laser device, immediately before burying regrowth of a diffraction grating, halogen-based gas is introduced to a reactor, and etching is performed on the diffraction grating so that each side wall has at least two or more crystal faces and a ratio of length of an upper side in a waveguide direction to a bottom side parallel to a (100) surface is 0 to 0.3. And, a reactive product formed on side surfaces of the diffraction grating and in trench portions between stripes of the diffraction grating at an increase of temperature for regrowth is removed. Therefore, the diffraction grating with reduced height and a sine wave shape is obtained, thereby ?L of the device is reduced. Thus, an oscillation threshold and optical output efficiency can be improved.

Abstract: A test circuit for, and method of, determining electrical properties of an underlying interconnect layer and an overlying interconnect layer of an integrated circuit (IC) and an IC incorporating the test circuit or the method. In one embodiment, the test circuit includes a gate chain having a ring path and a stage. In one embodiment, the stage includes: (1) a underlying test segment in the underlying interconnect layer, (2) a overlying test segment in the overlying interconnect layer and (3) logic circuitry activatible after formation of the underlying interconnect layer and before formation of the overlying interconnect layer to place the underlying test segment in the ring path and further activatible after the formation of the overlying interconnect layer to substitute the overlying test segment for the underlying test segment in the ring path.

Abstract: A semiconductor device includes a substrate and a channel region which is formed above the substrate by printing, wherein a relationship L?2a is satisfied where L is a channel length of the channel region and a is a minimum dimension among pattern dimensions and inter-pattern dimensions in the same layer as patterns that define the channel length L; and a relationship W?2b is satisfied where W is a channel width of the channel region and b is a minimum dimension among pattern dimensions and inter-pattern dimensions in the same layer as a pattern that defines the channel width W.