Abstract: A photoconductive device that generates or detects terahertz radiation includes a semiconductor layer; a structure portion; and an electrode. The semiconductor layer has a thickness no less than a first propagation distance and no greater than a second propagation distance, the first propagation distance being a distance that the surface plasmon wave propagates through the semiconductor layer in a perpendicular direction of an interface between the semiconductor layer and the structure portion until an electric field intensity of the surface plasmon wave becomes 1/e times the electric field intensity of the surface plasmon wave at the interface, the second propagation distance being a distance that a terahertz wave having an optical phonon absorption frequency of the semiconductor layer propagates through the semiconductor layer in the perpendicular direction until an electric field intensity of the terahertz wave becomes 1/e2 times the electric field intensity of the terahertz wave at the interface.

Abstract: A three-dimensional NAND device includes a first set of word line contacts in contact with a contact portion of respective odd numbered word lines in a first stepped word line contact region, and a second set of word line contacts in contact with a contact portion of respective even numbered word lines in a second stepped word line contact region. The even numbered word lines in the first word line contact region do not contact a word line contact while the odd numbered word lines in the second word line contact region do not contact a word line contact.

Abstract: A display device with low manufacturing cost, a display device with low power consumption, a display device capable of being formed over a large substrate, a display device with a high aperture ratio of a pixel, and a display device with high reliability are provided. The display device includes a transistor electrically connected to a light-transmitting pixel electrode and a capacitor. The transistor includes a gate electrode, a gate insulating film, and a first multilayer film including an oxide semiconductor layer. The capacitor includes the pixel electrode and a second multilayer film overlapping with the pixel electrode, positioned at a predetermined distance from the pixel electrode, and having the same layer structure as the first multilayer film. A channel formation region of the transistor is at least one layer, which is not in contact with the gate insulating film, of the first multilayer film.

Abstract: Methods of lithographic patterning and structures formed by lithographic patterning. A hardmask layer is formed on a dielectric layer, a feature is formed on the hardmask layer, and a mandrel is formed that extends in a first direction across the first feature. The mandrel and the hardmask layer beneath the mandrel are removed to pattern the hardmask layer with the feature masking a section of the hardmask layer. After the hardmask layer is patterned, the dielectric layer is etched to form a first trench and a second trench that are separated by a section of the dielectric layer masked by the section of the hardmask layer. The first trench and the second trench are filled with a conductor layer to respectively form a first wire and a second wire that is separated from the first wire by the section of the dielectric layer.

Abstract: A system and method for fabricating non-planar devices while managing short channel and heating effects are described. A semiconductor device fabrication process includes forming a non-planar device where the body of the device is insulated from the silicon substrate, but the source and drain regions are not insulated from the silicon substrate. The process builds a local silicon on insulator (SOI) while not insulating area around the source and drain regions from the silicon substrate. A trench is etched a length at least that of a channel length of the device while being bounded by a site for a source region and a site for a drain region. The trench is filled with relatively thick layers to form the local SOI. When nanowires of a gate are residing on top of the layer-filled trench, a second trench is etched into the top layer for depositing gate metal in the second trench.

Abstract: A silicon controlled rectifier, an electrostatic discharge (ESD) protection circuit including the silicon controlled rectifier and an integrated circuit including the silicon controlled rectifier or ESD protection circuit. The silicon controlled rectifier includes a first region having a first conductivity type and a second region having a second conductivity type located adjacent the first region in a semiconductor substrate. A junction is formed at a boundary between the first region and the second region. Contact regions of the first conductivity type and the second conductivity type located in each of the first region and the second region. A further contact region of the second conductivity type is located in the second region, in between the contact region of the first conductivity type and the junction. The further contact region and the contact region of the second conductivity type in the second region are connected together for biasing the second region.

Abstract: An IGBT includes a rectangular trench including first to fourth trenches and a gate electrode arranged inside of the rectangular trench. An n-type emitter region includes a first emitter region being in contact with the first trench, and a second emitter region being in contact with the third trench. A body contact region includes a first body contact region being in contact with the second trench, and a second body contact region being in contact with the fourth trench. A surface body region is in contact with the trenches in ranges from connection portions to the emitter regions.

Abstract: The following configuration is adopted in order to provide a highly reliable optival sensor device which enhances the reliability of devices without making the devices unsuitable for size and thickness reductions. The light sensor comprises an element-mounting portion (3) having a cavity and a lid member closely attached thereinto, the lid member being composed of: a window (2) constituted of a phosphate-based glass to which properties approximate to a spectral luminous efficacy properties have been imparted by compositional control; and a frame (1) constituted of a phosphate-based glass having light-shielding properties.

Abstract: Optically sensitive devices include a device comprising a first contact and a second contact, each having a work function, and an optically sensitive material between the first contact and the second contact. The optically sensitive material comprises a p-type semiconductor, and the optically sensitive material has a work function. Circuitry applies a bias voltage between the first contact and the second contact. The optically sensitive material has an electron lifetime that is greater than the electron transit time from the first contact to the second contact when the bias is applied between the first contact and the second contact. The first contact provides injection of electrons and blocking the extraction of holes. The interface between the first contact and the optically sensitive material provides a surface recombination velocity less than 1 cm/s.

Abstract: An organic light emitting display device comprising: a substrate; a display area on the substrate; and an encapsulation layer disposed on the display area and comprising a plurality of inorganic layers and a plurality of organic layers, wherein the plurality of inorganic layers and the plurality of organic layers are alternately laminated, the inorganic layer comprises at least first to third inorganic layers, the organic layer comprises at least first and second organic layers, the first inorganic layer is disposed on the display area, the first organic layer is disposed on the first inorganic layer, the second inorganic layer is disposed on the first organic layer and covers end portions of the first inorganic layer, the second organic layer is disposed on the second inorganic layer, and the third inorganic layer is disposed on the second organic layer and does not contact the second inorganic layer.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of : providing a substrate; forming a first gate structure on the substrate; forming a first contact plug adjacent to the first gate structure; and performing a replacement metal gate (RMG) process to transform the first gate structure into metal gate.

Abstract: A transistor with favorable electrical characteristics, a transistor with stable electrical characteristics, or a highly integrated semiconductor device is provided. In a top-gate transistor in which an oxide semiconductor is used for a semiconductor layer where a channel is formed, elements are introduced to the semiconductor layer in a self-aligned manner after a gate electrode is formed. After that, a side surface of the gate electrode is covered with a structure body. The structure body preferably contains silicon oxide. A first insulating layer is formed to cover the semiconductor layer, the gate electrode, and the structure body. A second insulating layer is formed by a sputtering method over the first insulating layer. Oxygen is introduced to the first insulating layer when the second insulating layer is formed.

Abstract: An apparatus relates generally to a microelectronic device. In such an apparatus, a first substrate has a first surface with first interconnects located on the first surface, and a second substrate has a second surface spaced apart from the first surface with a gap between the first surface and the second surface. Second interconnects are located on the second surface. Lower surfaces of the first interconnects and upper surfaces of the second interconnects are coupled to one another for electrical conductivity between the first substrate and the second substrate. A conductive collar is around sidewalls of the first and second interconnects, and a dielectric layer is around the conductive collar.

Abstract: An array substrate and manufacturing method thereof, a display device are provided. The array substrate includes a display region and a non-display region; the non-display region includes a first laminated structure and a second laminated structure that are separately disposed on a base substrate, a gap between the first laminated structure and the second laminated structure constitutes a connecting hole; the first laminated structure includes a first via hole provided for exposing a first metal layer, the second laminated structure includes a second via hole provided for exposing a second metal layer, the first via hole and the second via hole are connected to a connecting hole via breaches on corresponding walls, and the first metal layer and the second metal are electrically connected with a conductive film.

Abstract: According to various embodiments, a method may include: disposing a dopant in a semiconductor region; forming a radiation absorption layer including or formed from at least one allotrope of carbon over at least a portion of the semiconductor region; and activating the dopant at least partially by irradiating the radiation absorption layer at least partially with electromagnetic radiation to heat the semiconductor region at least partially.

Abstract: A light emitting device package is provided. The package includes a light emitting device including a substrate, and a light emitting structure having a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer stacked on the substrate; and a wavelength conversion film disposed in a path of light emitted by the light emitting device and having phosphor layers stacked on each other. A portion of the phosphor layers includes phosphor structures including a wavelength conversion material receiving light emitted from the light emitting device and converting a wavelength thereof and a binding resin binding the wavelength conversion material, and a transparent resin filling spaces between the phosphor structures.

Abstract: A portion of a charge trapping layer adjacent to a select drain gate electrode can be removed employing a differential-rate etch process that provides an accelerated etch rate to a doped portion with respect to an undoped portion. If a silicon nitride layer is employed as the charge trapping layer, then angled ion implantation of boron atoms to an upper portion of the silicon nitride layer can increase the etch rate of the boron-doped portion of the silicon nitride layer in phosphoric acid. The charge trapping layer is etched back such that a remaining portion of the charge trapping layer can be present only at levels of control gate electrodes, and absent at each level of select drain gate electrodes. Threshold voltage shift for the select drain gate electrodes can be eliminated or reduced by removal of the charge trapping layer at each level of the select drain gate electrodes.

Abstract: A method for fabricating a Polysilicon Thin-Film Transistor is provided. The method includes forming a polysilicon active layer, forming a first gate insulation layer and a first gate electrode sequentially on the active layer, conducting a first ion implantation process on the active layer by using the first gate electrode as a mask to form two doped regions at ends of the active layer, forming a second gate insulation layer and a second gate electrode sequentially on the first gate insulation layer and the first gate electrode, and conducting a second ion implantation process on the active layer by using the second gate electrode as another mask to form two source/drain implantation regions at two outer sides of the doped regions of the active layer. Accordingly, impurity concentration of the two doped regions is smaller than that of the two source/drain implantation regions.

Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.

Abstract: A circuit includes a conductive clip coupled to at least one component in the circuit. At least one lead portion is located on an end of the clip. The circuit further includes a first lead frame having at least one opening sized to receive the at least one lead portion. The at least one lead portion is received in the at least one opening and the at least one lead portion is an external conductor of the circuit.