Abstract: Managing a cache includes parsing a physical address of a data block to determine a partition identifier (ID) and a tag; the partition ID compared against a partition table storing partition IDs. The partition table indicates at least one way partition and at least one set partition corresponding to the partition ID. Based on the partition table, a way partition is determined at which to store the data block, corresponding to a subset of columns of a cache and, based on the partition table and the tag, a set partition is determined at which to store the data block, corresponding to a subset of rows of the cache. A cache address is generated for the data block within a first region of the cache corresponding to an intersection of the way partition and the set partition. The data block is stored to the cache according to the cache address.

Abstract: Systems and methods for managing queue limit overflow for data storage device arrays are described. Host storage connections are allocated by host connection identifier and storage device processing queues are allocated by completion connection identifier through a connection virtualization layer. Storage commands may be directed to a processing queue based on the host connection identifier. Responsive to determining that the processing queue has reached its queue depth limit, another processing queue is determined for receiving the storage command without indicating processing queue overflow to the host device.

Abstract: A master request comprising a plurality of bits is received, each bit representing whether a host device of a plurality of host devices has issued a memory access request. The master request is divided into a plurality of slices, each respective slice containing a subset of the plurality of bits corresponding a subset of host devices. Based on the respective subsets of the plurality of bits, it is determined whether each respective slice contains at least one memory access request. A first round robin process then begins in which it is determined whether each respective slice contains a memory access request. If so, any memory access request contained in the respective slice are processed via a second round robin process before proceeding to process memory access requests of another slice. If the respective slice contains no memory access requests, processing skips to a next slice without processing the respective slice.

Abstract: Techniques for data writing involve: determining an unavailable storage zone in multiple storage zones of a storage area, wherein each storage zone is used to store a zip header and compressed data corresponding to the zip header; acquiring a reference zip header for the unavailable storage zone, wherein the reference zip header includes metadata indicating a zone length of the unavailable storage zone; and generating consecutive write requests for the storage area based at least on target data to be written to the storage area and the reference zip header, so as to write the target data to available storage zones in the multiple storage zones. Accordingly, rewriting of data can be implemented by constructing large consecutive write requests, thus improving the write performance of the storage device.

Abstract: Subject matter disclosed herein relates to management of a memory device.

Abstract: A controller for controlling memory devices is provided to include: a first core configured to control first memory devices in communication with the controller and configured to store data associated with first logical addresses; a second core configured to control second memory devices in communication with the controller and configured to store data associated with second logical addresses; and a host interface configured to (1) queue commands received from a host in a queue, (2) perform a command reordering that determines a processing order of queued commands including a first address command associated with a first logical address and a second address command associated with a second logical address based on statuses of the first memory devices and the second memory devices, and (3) provide the first address command to the first core and the second address command to the second core based on the processing order.

Abstract: In one aspect, adaptive replication modes in a storage system are provided. An aspect includes during an active replication session in which a first type of replication is performed at the storage system, monitoring write input/output (IO) operations, collecting data from the write IO operations, and determining, from the collected data, write IO latency. Upon determining that a threshold value has been met from the write IO latency, where the threshold value is defined for the first type of replication, an aspect includes automatically switching from the first type of replication to a second type of replication. The second type of replication is configured to compensate for operational deficiencies detected in response to the write IO latency.

Abstract: A gateway for interfacing a host with a subsystem for acting as a work accelerator to the host. The gateway enables the transfer of batches of data to the subsystem at precompiled data exchange synchronisation points. The gateway acts to route data between accelerators which are connected in a scaled system of multiple gateways and accelerators using a global address space set up at compile time of an application to run on the computer system.

Abstract: Systems, apparatuses, and methods for implementing a memory fetch granule for real-time agents are described. A computing system includes a plurality of real-time agents coupled to memory via an interconnect fabric and a memory controller. The efficiency of the memory controller is determined by the number of bank groups in the memory devices coupled to the memory controller. A memory fetch granule is defined for the memory controller based on the amount of data that can be accessed in parallel on the memory device in back-to-back access cycles. Each real-time agent accumulates memory requests for sequential physical addresses until the amount of data referenced by the requests reaches the size of the memory fetch granule. Once the memory fetch granule is reached, the real-time agent sends the requests to the memory controller via the fabric. This helps to ensure that the requests will arrive at the memory controller near enough to each other to get grouped together.

Abstract: The disclosure relates in some aspects to managing the fetching and execution of commands stored in submission queues. For example, execution of a command may be blocked at a data storage apparatus due to an internal blocking condition (e.g., a large number of commands of a particular type are pending for execution at the data storage device). As another example, execution of a command may be blocked at a data storage apparatus due to an external blocking condition (e.g., a host device may specify that certain commands are to be executed immediately one after another). The disclosure relates in some aspects to controlling how commands are fetched and executed so that commands that cannot be executed by the data storage apparatus in the near future do not prevent other commands (that are not subject to the same blocking condition) from being executed.

Abstract: Disclosed herein is a redundancy resource comparator for a bus architecture of a memory device for comparing an address signal being received from an address signal bus and a redundancy address being stored in a latch of the memory device. Disclosed is also a corresponding bus architecture and comparison method.

Abstract: A device, memory, method and system directed to fast data storage on a block storage device that reduces operational wear on the device. New data is written to an empty write block with a number of write blocks being reused. A location of the new data is tracked. Metadata associated with the new data is written. A lookup table may be updated based in part on the metadata. The new data may be read based the lookup table configured to map a logical address to a physical address.

Abstract: Disclosed in some examples are methods, systems, memory controllers, devices, and machine-readable mediums which minimize this stall time by returning a memory write acknowledgement once a write command has been selected by the memory controller input multiplexor rather than when the memory write command has been performed. Because the memory controller enforces an ordering to memory once the packet has been selected at an input multiplexor, ordering of prior and subsequent requests to the same address location are preserved and providing the response early allows the processor to continue its operations earlier without any harmful effects.

Abstract: Disclosed herein are system, method, and computer program product embodiments for performing fair prefetching. An embodiment operates by splitting a data vector into a first subrange and a second subrange. The embodiment performs a first chance prefetch operation on the first subrange based on a fixed number of pages, thereby loading a set of pages of the first subrange into a main memory. The embodiment performs the first chance prefetch operation on the second subrange based on the fixed number of pages, thereby loading a first set of pages of the second subrange into the main memory. The embodiment performs a second chance prefetch operation on the second subrange based on the performing the first chance prefetch operation on the second subrange, thereby loading a second set of pages of the second subrange into the main memory. The embodiment then executes the query.

Abstract: Techniques and mechanisms for providing communications which facilitate link training. In an embodiment, a memory controller includes, or couples to, trainer circuitry which is configured to provide instructions to generate memory access commands. The instructions are accessed at the circuitry in response to an indication that link training is performed, where the accessing is independent of communication with a processor coupled to the memory controller. Based on the instructions, memory access commands are communicated via a link between the memory controller and a memory device. Link training is performed based on an evaluation of one or more characteristics of the link communications. In another embodiment, memory access commands are generated, based on the instructions, while a validity of data at the memory device is maintained.

Abstract: Examples of the present disclosure provide apparatuses and methods for span mask generation. An example method comprises creating, using sensing circuitry, a number of bit vectors, wherein each of the number of bit vectors includes a repeating pattern based on a size of the number of bit vectors and a particular mask depth.

Abstract: Disclosed herein is a thin-provisioned multi-node computer system with a disaggregated memory pool and a pooled memory controller. The disaggregated memory pool is configured to make a shared memory capacity available to each of a plurality of compute nodes, such memory capacity being thinly provisioned relative to the plurality of compute nodes. The pooled memory controller is configured to assign a plurality of memory segments of the disaggregated memory pool to the plurality of compute nodes; identify a subset of the plurality of segments as cold segments, such identification being based on determining that a usage characteristic for each such cold segment is below a threshold; and page one or more of the cold segments out to an expanded bulk memory device, thereby freeing one or more assigned memory segments of the disaggregated memory pool.

Abstract: A computer-implemented method of resizing a data structure includes storing a first hash index comprising x elements, wherein x is a positive integer greater than two, determining that the first hash index needs to expand, allocating a second hash index, wherein the second index contains at least x+1 elements, attempting, by a first thread, to advance a first pointer from the first hash index to the second hash index, attempting, by a second thread, to advance the first pointer from the first hash index to the second hash index, where only one of the first thread or the second thread will advance the first pointer based on an atomic operation.

Abstract: Apparatuses and methods related to a memory module controller are disclosed. An example apparatus, such as a dual in-line memory module (DIMM), includes a first interface coupled to a host, and a second interface coupled to another memory module. The memory module includes a controller configured to simultaneously communicate with the host via the first interface, which may be a non-volatile DIMM (NVDIMM) interface in one example, and communicate with the other memory module via the second interface. In some examples, the first and second interfaces are configured according to different standards or protocols. The controller controls access to memory on the memory module. The controller may be configured to receive commands from a direct memory access (DMA) module. In some examples, the other memory module connected via the second interface includes a local controller and memory of a different type.

Abstract: A method for managing a plurality of storage devices includes obtaining, by a storage device cleaning manager, a set of self-monitored statistics, performing an initial concern analysis to generate an initial concern prediction for each of the plurality of storage devices in a storage system, wherein the set of self-monitored statistics are associated with the plurality of storage devices, updating a cleaning policy based on the initial concern prediction, obtaining input/output (I/O) statistics, after updating the cleaning policy based on the initial concern prediction, performing a secondary concern analysis using the I/O statistics to generate a secondary concern prediction for each of the plurality of storage devices, wherein the I/O statistics are associated with the plurality of storage devices, further updating the cleaning policy, and performing a cleaning of at least a portion of the plurality of storage devices based on the updated cleaning policy.