Abstract: Devices and techniques for generating a response to a host with a memory device are provided. A first command from a host can be executed. A status for the first command can be determined. An inquiry from the host about a second command can be received after execution of the first command has begun. A response can be made to the inquiry that includes information about the second command and the status for the first command.

Abstract: A method of indirection replay for a flash storage system includes writing data, in a host stream, to blocksets of the flash storage system. The host blocksets are assigned a major sequence number incremented from the most recently closed host blockset. The method includes writing an indirection journal to each host blockset which are associated with the assigned major sequence number. The method includes writing data, in a garbage collection (GC) stream, to other blocksets of the flash storage system. The GC blocksets are assigned a major sequence number, based on the most recently closed host blockset, and a minor sequence number, incremented from the most recently closed GC blockset. The method includes writing an indirection journal to each GC blockset which are associated with the assigned major and minor sequence numbers. The indirection table is constructed by replaying the journals of the blocksets in order of major sequence and minor sequence numbers.

Abstract: In general, the invention relates to a method for processing data. The method includes receiving a write request from a host, and in response to the write request, obtaining system metadata for a system, selecting, based on the system metadata, a selected component of the system to perform a data processing operation, and initiating the data processing operation on the selected component.

Abstract: A method, computer program product, and computer system for receiving, by a computing device, new data to write to a leaf. At least two timestamps of the leaf may be examined. It may be determined whether a time interval between the at least two timestamps of the leaf is greater than an age threshold. The new data may be written to a first tier storage device when the time interval between the at least two timestamps of the leaf is less than the age threshold; The new data may be written to a second tier storage device when the time interval between the at least two timestamps of the leaf is greater than the age threshold.

Abstract: A processor including a logic unit configured to execute multiple instructions being one of a speculative instruction or an architectural instruction is provided. The processor also includes a split cache comprising multiple lines, each line including a data accessed by an instruction and copied into the split cache from a memory address, wherein a line is identified as a speculative line for the speculative instruction, and as an architectural line for the architectural instruction. The processor includes a cache manager configured to select a number of speculative lines allocated in the split cache. The cache manager prevents an architectural line from being replaced by a speculative line based on a number of speculative lines allotted in the split cache, and manages the number of speculative lines to be allocated in the split cache based on the number of speculative lines relative to a number of architectural lines.

Abstract: A computer-implemented method, according to one embodiment, includes: receiving, by a computer, a data access request; sending, by the computer, a recall request to a remote storage location for data which corresponds to the data access request; and receiving, by the computer, a copy of an existing object which includes blocks. The data which corresponds to the data access request is stored in at least one of the blocks. The data access request is satisfied, by the computer, by providing the copy of the existing object. Moreover, a sparse object, which only includes ones of the blocks which contain data that has been modified, is received by the computer. The sparse object is sent, by the computer, to the remote storage location; and one or more instructions to use the blocks included in the sparse object to update the existing object are also sent by the computer.

Abstract: Provided are a method, system, and computer program product in which a storage controller receives a request from a host to migrate a source dataset comprising a plurality of tracks to a cloud storage. A plurality of readers are initiated to read the plurality of tracks of the source dataset in parallel, wherein each of the plurality of readers reads different tracks from the source dataset and transmits the tracks that are read from the source dataset to a migrator. For each track received by the migrator from the plurality of readers, the track is appended sequentially to a migrate dataset to be stored in the cloud storage. Metadata that indicates a mapping of tracks of the source dataset to tracks of the migrate dataset is generated.

Abstract: A semiconductor memory device includes a memory region including a plurality of memory blocks, and suitable for outputting first and second read data from first and second memory blocks among the plurality of memory blocks based on first and second read control signals and a read address signal; a scheduler suitable for outputting a read scheduling signal based on the first and second read control signals; and an output driver suitable for outputting the first and second read data by a predetermined burst length alternately twice or more to a data pad based on a mode signal, wherein the first read data are outputted to the data pad according to a first burst sequence, and the second read data are outputted to the data pad according to a second burst sequence, based on the read scheduling signal.

Abstract: A computing system is disclosed herein. The computing system includes a computing node and a remote memory node coupled to the computing node via a system fabric. The computing node includes a plurality of processors and a master memory controller. The master memory controller is external to the plurality of processors. The master memory controller routes requests corresponding to requests from the plurality of processors across the system fabric to the remote memory node and returns a response.

Abstract: A technique for determining a data window size allows a set of predicted blocks to be transmitted along with requested blocks. A stream enabled application executing in a virtual execution environment may use the blocks when needed.

Abstract: A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path.

Abstract: Communicating with a tape drive emulation unit that communicates using command mode or transport mode includes the tape drive emulation unit receiving an inquiry about whether the tape drive emulation unit communicates using transport mode, the tape drive emulation unit responding to the inquiry by indicating that the tape drive emulation unit does communicate using transport mode, and the tape drive emulation unit servicing transport mode commands until receiving a release command. The tape drive emulation unit may include a front end component, a data mover/server, and a tape emulation storage device. The data mover/server may include an NFS server. A host may communicate with the tape emulation unit. The host and the tape emulation unit may be coupled using a FICON connection. A host application may send commands to the tape emulation unit and may receive commands from the tape emulation unit using command mode.

Abstract: A cache controller with a pattern recognition mechanism can identify patterns in cache lines. Instead of transmitting the entire data of the cache line to a destination device, the cache controller can generate a meta signal to represent the identified bit pattern. The cache controller transmits the meta signal to the destination in place of at least part of the cache line.

Abstract: There is provided an apparatus that includes a first port that receives first data of a first type from a first storage circuit. A second port receives second data of a second type from a second storage circuit having a lower worst case latency in hardware than the first storage circuit. A third port receives access requests for the first data and the second data from a processing circuit. When one of the access requests is received for the first data, it is forwarded to the first storage circuit and when the one of the access requests is received for the second data, it is forwarded to the second storage circuit. A shared storage circuit stores the first data and the second data and has a storage capacity.

Abstract: Embodiments of the inventions are directed towards a computer-implemented methods and systems for determining an oldest logical memory address. The method includes creating an M number of miss request registers and an N number of stations in a load/store unit of the processor. In response to load requests from target instructions, a processor detects each L1 cache miss. The processor stores data related to each L1 cache miss in a respective miss request register. The data includes an age of each L1 cache miss and a portion of a logical memory address of the requested load. The processor stores the entire logical memory addresses of the requested loads in respective stations based on an age of the load requests. The processor transmits the oldest logical memory address that is stored at the stations.

Abstract: A nonvolatile memory device may include: a memory cell array operated by a first voltage, and including a plurality of memory cells; a peripheral circuit operated by the first voltage, and configured to store data in the memory cell array or read data from the memory cell array; an operation recorder operated by a second voltage, and configured to record information on an operation being performed in the nonvolatile memory device; and a control logic operated by the first voltage, and configured to control the peripheral circuit such that the nonvolatile memory device performs an operation corresponding to a command received from an external device, and control the operation recorder to store the information on the operation being performed in the nonvolatile memory device.

Abstract: A memory system may include a first memory device including a first input/output buffer, a second memory device including a second input/output buffer, and a cache memory suitable for selectively and temporarily storing first and second data to be respectively programmed in the first and second memory devices. The first data is programmed to the first memory device in a first program section by being stored in the cache memory only in a first monopoly section of the first program section. The second data is programmed to the second memory device in a second program section by being stored in the cache memory only in a second monopoly section of a second program section. The first monopoly section and the second monopoly section are set not to overlap each other.

Abstract: In one aspect, adaptive replication modes in a storage system are provided. An aspect includes during an active replication session in which a first type of replication is performed at the storage system, monitoring write input/output (IO) operations, collecting data from the write IO operations, and determining, from the collected data, write IO latency. Upon determining that a threshold value has been met from the write IO latency, where the threshold value is defined for the first type of replication, an aspect includes automatically switching from the first type of replication to a second type of replication. The second type of replication is configured to compensate for operational deficiencies detected in response to the write IO latency.

Abstract: A memory system includes a nonvolatile memory that has a plurality of physical blocks, and a memory controller circuit configured to execute encoding of data to be written in the nonvolatile memory and decoding of data read from the nonvolatile memory, execute garbage collection for the nonvolatile memory, and determine whether or not decoding and encoding is to be executed, for data which is read from a valid cluster of a physical block targeted for garbage collection.

Abstract: Embodiments disclosed herein provide systems, methods, and computer-readable media to implement an object store with removable storage media. In a particular embodiment, a method provides identifying first data for storage on a first removable storage medium and designating at least a portion of the first data to a first data object. The method further provides determining a first location where to store the first data object in a first value store partition of the first removable storage medium and writing the first data object to the first location. Also, the method provides writing a first key that identifies the first data object and indicates the first location to a first key store partition of the first removable storage medium.