Abstract: According to one general aspect, an apparatus may include a processor, a heterogeneous memory system, and a memory interconnect. The processor may be configured to perform a data access on data stored in a memory system. The heterogeneous memory system may include a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with one or more performance characteristics. The heterogeneous memory system may include both volatile and non-volatile storage mediums. The memory interconnect may be configured to route the data access from the processor to at least one of the storage mediums based, at least in part, upon the one or more performance characteristic associated with the respective memory technologies of the storage media.

Abstract: A memory management method for a memory storage device including a rewritable non-volatile memory (RNVM) module is provided. The memory management method includes: receiving a plurality of commands; detecting a power glitch; and sending a command sequence which instructs the (RNVM) module to perform a first operation according to a first command among the plurality of commands and to ignore a second command among the plurality of commands after the power glitch occurs. A command queue may be scanned, and scanning may be suspended and the command queue resumed if a first-type command, such as an erase command or a write command, is found, or scanning continued if a second-type command, such as a read command, is found. A memory control circuit unit may proceed with a programming operation if it determines a write command is a non-full sequential programming command. Other commands may be suspended after a programming operation is completed according to a specific mark in a full sequential programming command.

Abstract: Hybrid intra-cluster migration of data in an elastic cloud storage (ECS) environment is disclosed herein. A system comprises a processor and a memory that stores executable instructions that, when executed by the processor, perform operations that include moving a first data chunk from a first storage device to a second storage device during a data migration, based on a first determination that a first use efficiency of the first data chunk satisfies a defined use efficiency threshold. The operations also include moving a first data segment from a second data chunk in the first storage device to a third data chunk in the second storage device during the data migration, based on a second determination that a second use efficiency of the second data chunk fails to satisfy the defined use efficiency threshold. The first data segment includes data that is open for new writes and a second data segment includes data that is not open for new writes. After data is moved, capacity of the first data chuck is recovered.

Abstract: An aspect of performing dual splitting functions in a data replication system include receiving an I/O from a host computer. The host computer includes a first splitter configured to perform control path functions. An aspect also includes adding, via the first splitter, metadata for the I/O to a backlog at the host computer, and sending the I/O to a storage array. The storage array includes a second splitter configured to perform data path functions. An aspect further includes receiving, by the storage array, the I/O from the host computer, and sending, via the second splitter, the I/O to at least one storage device of the storage array and to a data protection appliance (DPA). The control path functions include tracking I/Os and maintaining backlogs including the backlog at the host computer, and the data path functions include mirroring operations in the storage array.

Abstract: A solid state drive includes: a plurality of non-volatile memories, each of the non-volatile memories connected to a channel, the channel connected to at least one way connected to a die; a host interface which receives stream data and stream information from a host; and a resource allocator which allocates the stream data to super blocks of the plurality of non-volatile memories on the basis of the stream information. A super block includes a unit super block, and the unit super block includes a block of a first die corresponding to a first channel and connected to a plurality of the ways connected to the first channel. The stream data may include stream groups, and the stream information may include the number of streams included in a stream group. A performance factor of a stream or stream group an extent size of a stream, and an allocation position of the stream, may also be included in the stream information.

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

Abstract: An apparatus comprises a storage system having storage devices and an associated storage controller. In conjunction with initiation of a checkpoint, the storage controller sets a checkpoint started flag for the checkpoint, marks user data pages and metadata pages for write operations already entered in a write journal of the storage system as of the setting of the checkpoint started flag as checkpoint pages, and marks user data pages and metadata pages for new write operations entered in the write journal after the setting of the checkpoint started flag as non-checkpoint pages by altering information used to generate signatures for respective ones of the metadata pages. Metadata pages characterizing the same user data pages subject to write operations at different times thereby have different signatures depending on whether or not the checkpoint started flag was set when its corresponding write operation was entered in the write journal.

Abstract: Resource management includes: operating in a first mode, including executing a controller operation in connection with a plurality of local elements, wherein the controller operation is executed by a configurable resource; switching from the first mode to a second mode; and operating in the second mode, including: executing a data processing task in a first portion of the configurable resource; and executing the controller operation in connection with the plurality of local elements, in a second portion of the configurable resource.

Abstract: Disclosed is an apparatus including a memory system. The memory system includes a controller that assigns a first PEC to a first metablock based on a first number of structures of a memory across which the first metablock is distributed. The controller assigns a second PEC to a second metablock based on a second number of the structures of the memory across which the second metablock is distributed. The controller selects one of the first metablock or the second metablock to be used based on the first PEC and the second PEC.

Abstract: The flash memory system according to the embodiment of the present invention is characterized by programming a selected page in a quantization signal generating operation, providing a reference read voltage to a selected word line connected to the selected page, A flash memory for generating a flash memory; And a memory controller for receiving a quantized signal from the flash memory and generating a response using the quantized signal, wherein the memory controller receives an challenge from a host and the flash memory performs the quantized signal generation.

Abstract: Methods, systems, and devices for activity-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include determining a quantity of access operations performed on a set of sections of a memory device, selecting at least one of the sections for a voltage adjustment operation, such as an equalization operation or a dissipation operation, based on the determined quantity of access operations, and performing the voltage adjustment operation on the selected section. Selecting one of the memory sections for a voltage adjustment operation may also be based on a timer. Equalizing a bias may include biasing a plate line, which may be coupled to a ferroelectric capacitor of a memory cell, to a ground voltage or some non-zero voltage.

Abstract: An apparatus and method are described for implementing a hybrid layer of address mapping for an IOMMU implementation.

Abstract: An uneven distributed storage across a mesh fabric storage system may include receiving storage operations from one or more client devices and/or applications contemporaneously with receiving availability messaging from a set of multiple storage devices that may be of the same or different types. One or more of the storage operations may be assigned to a storage device that has signaled its readiness to perform the one or more storage operations via an issued availability message. Each storage device may thereby perform a subset of the collective set of storage operations with the uneven distribution allocating load that is directly commensurate with the performance of each storage device. Stored data may be moved between storage devices using a similar availability-driven methodology so as to reallocate capacity usage while still providing the fastest storage performance associated with all storage devices writing the data as it is generated.

Abstract: Disclosed herein is an apparatus configured to log transactions of a translation lookaside buffer (TLB) into a software-accessible buffer. The apparatus includes a memory management unit (MMU) configured to translate a logical memory address to a physical memory address for accessing a physical memory. The apparatus also includes a TLB configured to store a plurality of entries, where each entry includes a logical memory page address and an associated physical memory page address. The apparatus further includes a software-accessible buffer and a TLB event logging circuit configured to detect an event associated with an entry of the TLB and store information regarding the detected event in the software-accessible buffer.

Abstract: Systems, methods, and devices can include a processing engine implemented at least partially in hardware, the processing engine to process memory transactions; a memory element to index physical address and virtual address translations; and a memory controller logic implemented at least partially in hardware, the memory controller logic to receive an index from the processing engine, the index corresponding to a physical address and a virtual address; identify a physical address based on the received index; and provide the physical address to the processing engine. The processing engine can use the physical address for memory transactions in response to a streaming workload job request.

Abstract: An apparatus, system, and method of enforcing cache coherency in a multiprocessor shared memory system are disclosed. A request is received from a node controller, to process a cache coherent operation on a memory block in a shared memory. Based on the information included in the request, a determination is made as to whether the request was transmitted from a processor that is remote relative to the memory that includes the memory block referenced in the request. If the request is from a remote processor, a hardware-based cache coherency of the system is disabled, and request is processed according to software-based cache coherency protocols and mechanisms. A coherent read request may be translated to a non-coherent request, such as an immediate read request, which does not trigger tracking or storing state and ownership information of the requested memory block, or trigger communications with processors other than those involved with request.

Abstract: A storage system is configured to comprise a processor in operable communication with a storage device and a metadata journal comprising metadata configured to store information associated with a change to be made to information stored on the storage device. While the storage system is booted up and responsive to I/O requests from a host, a scan is performed of a first portion of metadata that is loaded into storage system memory during the bootup, to check for existence of a metadata inconsistency condition comprising at least one of: (a) dirty tree (DT) entries in the metadata associated with an invalid logical unit (LU) index; (b) hash tree (HT) entries in the metadata which do not have corresponding DT bits; and (c) DT bits set without having a corresponding HT entry. Based on the results of the first scan, a determination is made about whether a first metadata inconsistency condition exists.

Abstract: Computing device and method for inferring a predicted number of physical blocks erased from a flash memory. The computing device stores a predictive model generated by a neural network training engine. A processing unit of the computing device executes a neural network inference engine, using the predictive model for inferring the predicted number of physical blocks erased from the flash memory based on inputs. The inputs comprise a total number of physical blocks previously erased from the flash memory, an amount of data to be written on the flash memory, and optionally an operating temperature of the flash memory. In a particular aspect, the flash memory is comprised in the computing device, and an action may be taken for preserving a lifespan of the flash memory based at least on the predicted number of physical blocks erased from the flash memory.

Abstract: A method is disclosed comprising: generating a plurality of snapshots, each of the snapshots representing a state of one or more storage objects in a storage system; generating a plurality of access pattern records (APRs) for the storage objects, each APR being associated with a different respective one of the plurality of snapshots, each APR indicating a characteristic of workload of the storage system in a period preceding the generation of the APR's associated snapshot; detecting a workload trend for the storage objects, the workload trend being detected by using a workload prediction model that is trained based on the plurality of APRs; and configuring the storage system based on the workload trend, the configuring including allocating additional resources for servicing access requests to the storage objects when the workload trend is a rising workload trend.

Abstract: A method, computer program product, and computer system are disclosed that in one or more embodiments includes issuing, from an issuing processor in the computer system, an address translation invalidation instruction with a return marker, wherein the address translation invalidation instruction is to invalidate one or more address translation entries in one or more storage locations in the computer system and wherein the return marker comprises an instruction to return information to the issuing processor indicating the identity of each processor where an invalidated entry was located.