Abstract: Technologies are provided for backing virtualization containers with layered storage volumes stored in remote storage devices. A virtualization container can present a virtual storage volume to a process running in the virtualization container and handle data access requests from the process using a layered storage volume based on one or more read-only snapshots stored in one or more remote storage devices. Changes can be recorded in a read-write layer in one or more of the remote storage devices and associated with the layered storage volume. A new read-only snapshot can be created based on the data in the read-write storage layer and associated with the one or more read-only snapshots on which the layered storage volume is based. A virtualization container can be associated with a new layered storage volume based on the created read-only snapshot and the one or more read-only snapshots on which it is based.

Abstract: Disclosed in some examples, are methods, systems, devices, and machine readable mediums that store instructions for programmable atomic transactions in a memory of the programmable atomic unit prior to execution of the programmable atomic transaction. The memory in some examples may be an instruction RAM. The memory in some examples may be partitioned into partitions of a fixed size that stores a same number of instructions. Each programmable atomic transaction may use one or more contiguously located instruction partitions. By loading the instructions ahead of time, the instructions are ready for execution when the transaction is requested.

Abstract: Methods and apparatus related to enabling individual NVMe (Non-Volatile Memory express) IO (Input Output or I/O) queues on differing network addresses of an NVMe controller are described. In one embodiment, a plurality of backend controller logic is coupled to a plurality of non-volatile memory devices. One or more virtual controller target logic (coupled to the plurality of backend controller logic) transmit data from a first portion of a plurality of IO queues to a first backend controller logic of the plurality of the backend controller logic. The one or more virtual controller target logic transmit data from a second portion of the plurality of IO queues to a second backend controller logic of the plurality of backend controller logic. Other embodiments are also disclosed and claimed.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may generate a nonce based on a physical address of a target area of a memory device using a cryptographic algorithm, and request the memory device to authenticate the nonce. When the authentication for the nonce succeeds, the memory controller may set an authority to perform a read, write or erase operation on the target area. Through this operation, the memory system can prevent data leakage or damage by a user who has no access authority.

Abstract: One embodiment provides a system including a computer processor, a computer-readable hardware storage device, and program code embodied with the computer-readable hardware storage device for execution by the computer processor to implement a method that includes receiving a selection of a first blob for reclamation from a first data center. The first blob includes multiple erasure code groups. A first message is sent to a second data center indicating the first blob is to be reclaimed. A global reclamation complete message is received from the second data center. The global reclamation complete message indicates a second blob in the second data center has been reclaimed. The first data center and the second data center each maintain local blob occupancy information.

Abstract: In an active-active system, if write lock permission is granted to a second storage array, a first storage array sends to-be-written data and a lock revocation request together to a lock server; the lock server sends a lock revocation request carrying the to-be-written data to the second storage array; after storing the to-be-written data, the second storage array sends a lock revocation success message to the lock server; the lock server gives the write lock permission to the first storage array; and the first storage array obtains the write lock permission and stores the to-be-written data.

Abstract: A storage device that provides in-storage transparent compression and implements a process for processing write requests during an out-of-space state. The process includes: receiving a write request from a host involving a set of logical block addresses (LBAs); determining if each of the LBAs in the write request is an actively used LBAs; and in response to determining that each of the LBAs in the write request are actively used LBAs, allowing the write request to be served; and in response to determining that at least one of the LBAs in the write request is not an actively used LBAs, not allowing the write request to be served and returning an error to the host.

Abstract: A network processor includes a memory subsystem serving a plurality of processor cores. The memory subsystem includes a hierarchy of caches. A mid-level instruction cache provides for caching instructions for multiple processor cores. Likewise, a mid-level data cache provides for caching data for multiple cores, and can optionally serve as a point of serialization of the memory subsystem. A low-level cache is partitionable into partitions that are subsets of both ways and sets, and each partition can serve an independent process and/or processor core.

Abstract: A memory access device includes: a data processor configured to output an access request requesting access to a memory connected to a data bus, perform a data processing on data in the accessed memory, and provide notification of a progress status of the data processing; a priority switching control part configured to determine an urgency of the data processing by the data processor according to the progress status of the data processing notified from the data processor, and output a priority switching signal notifying switching of a priority of the data processor; and a bus arbiter connected to the data bus, configured to change the priority of the data processor according to the priority switching signal to arbitrate the access request output from the data processor, and control access to the memory according to the access request that has been arbitrated.

Abstract: A data processing apparatus comprises processing circuitry to execute a plurality of processes. An ownership table comprises one or more entries each indicating, for a corresponding block of physical addresses, which of the processes is an owner process that has exclusive control of access to the corresponding block of physical addresses. A new process may be prevented from becoming an owner process until after successful completion of destructive overwriting. Ownership protection circuitry may detect a mismatch between an expected attribute, which is dependent on information in a page table entry, and an attribute specified in the ownership table. Each entry in the ownership table, for example, may indicate a level of encryption to be applied. Access control circuitry such as a memory management unit (MMU) may also determine whether an access request satisfies access permissions. The ownership table may also specify whether a higher privilege level process is allowed to access a block of physical addresses.

Abstract: Data collection is provided, in which one or more affected transactions related to one or more transaction exceptions are determined. Based on one or more features of the one or more affected transactions, one or more trace features are determined. Based on the one or more trace features, a data collection rule is generated. Data of a subsequent transaction complying with the data collection rule is collected.

Abstract: The data management device capable of calculating an evaluation index based on the sensor data includes: a sensor data acquisition unit that acquires the sensor data from one or more sensors installed in an industrial machine; an evaluation index calculation unit that calculates the evaluation index with use of the sensor data; a sensor data storage unit that saves the sensor data; and a sensor data deletion unit that deletes the sensor data when a total volume of the sensor data in the sensor data storage unit exceeds an upper limit. The sensor data deletion unit determines saving priority of the sensor data based on a degree of change in the evaluation index and deletes the sensor data in accordance with the saving priority.

Abstract: Aspects of a storage device including a memory and a controller are provided which allows for reduced latency of read-modify-write operations when a data length from a host is unaligned at two ends with a write length of the controller. When the controller receives from a host device a write command for data, the controller performs a first read of a head portion and a second read of a tail portion immediately after performing the first read. The controller performs a single L2P translation of one of the head or tail portions, senses the data associated with the head and tail portions once into latches, and reads the data from the latches for both the head and tail portions without performing another data sense. The controller then writes the data in response to the write command after performing the first read and the second read.

Abstract: A method for verification of content of tape cartridges in a tape library system using tape drives of the tape library, is provided. The method includes instructing the tape drive to perform tape cartridge verification on the tape cartridge. The method further includes after completion of the tape cartridge verification, unloading the tape cartridge to its original storage position. The method further includes transmitting verification data of the tape cartridge verification to a database of the tape library system for analysis.

Abstract: An electronic system such as an imaging system may include processing circuitry and memory circuitry. Data replacement circuitry may be interposed between the processing circuitry and the memory circuitry. In some implementations, the memory circuitry may be a read-only memory, and data replacement circuitry may be used to selectively replace executable firmware instructions stored on the read-only memory. The selective replacement operations may be based on an address that processing circuitry provides to access the memory circuitry. The data replacement circuitry may be implemented separately from the processing circuitry and the memory circuitry and may include a comparator block, registers, and switching circuitry.

Abstract: A distributed electronic storage system (DESS) comprises congestion management circuitry and data migration circuitry. The congestion management circuitry is operable to determine an amount of congestion in the DESS. The data migration circuitry is operable to control migration of data stored in a first tier of storage to a second tier of storage based on the amount of congestion in the DESS, characteristics of the data, and characteristics of the first tier of storage.

Abstract: Configuring parameters in backup environments is described. A system outputs, via a user interface, a backup environment question. The system receives, via the user interface, an answer to the backup environment question. The system configures a backup environment parameter based on the answer to the backup environment question and based on information extracted from a corresponding backup environment.

Abstract: A data processing system comprises a requesting node; a home node to control coherency amongst data stored by the data processing system; and one or more further nodes, at least one of the further nodes having a memory; the requesting node being configured to issue a data handling transaction to the home node, the data handling transaction defining a data handling operation relating to a range of memory addresses, the requesting node being configured to maintain an address hazard at the requesting node inhibiting issue of another data handling transaction for that range of memory addresses until the requesting node is notified by the home node that the data handling transaction has completed; the home node being configured, in response to the data handling transaction, to issue one or more data handling instructions to cause one or more given nodes of the one or more further nodes to perform the data handling operation, the home node being configured to notify completion to the requesting node in response to

Abstract: Memories that are configurable to operate in either a banked mode or a bit-separated mode. The memories include a plurality of memory banks; multiplexing circuitry; input circuitry; and output circuitry. The input circuitry inputs at least a portion of a memory address and configuration information to the multiplexing circuitry. The multiplexing circuitry generates read data by combining a selected subset of data corresponding to the address from each of the plurality of memory banks, the subset selected based on the configuration information, if the configuration information indicates a bit-separated mode. The multiplexing circuitry generates the read data by combining data corresponding to the address from one of the memory banks, the one of the memory banks selected based on the configuration information, if the configuration information indicates a banked mode. The output circuitry outputs the generated read data from the memory.

Abstract: A method comprises determining, in a process of storing data for a computing task of a first dedicated processing resource of a set of dedicated processing resources to the first dedicated processing resource, a size of an available space of a memory of the first dedicated processing resource; in response to the size of the available space of the memory of the first dedicated processing resource being lower than a predetermined threshold value, determining a second dedicated processing resource of the set of dedicated processing resources, a size of an available space of a memory of the second dedicated processing resource is greater than the predetermined threshold value; and causing at least one portion of the data not stored on the memory of the first dedicated processing resource to be stored on the memory of the second dedicated processing resource.