Abstract: A method for fabricating a body contact silicon-on-insulator transistor (10) includes forming a semiconductor substrate (12) over an insulator (14) and lightly doping the semiconductor substrate (12) to form a body region (18). The method also includes forming a gate (20) over the semiconductor substrate (12) and separated from the semiconductor substrate (12) by a gate insulator layer (21). The gate (20) defines a source region (22), a drain region (24) and a contact region (26). The method also includes masking a portion (36) of the gate (20) and the contact region (26) and heavily doping the source region (22), the drain region (24) and an unmasked portion (36) of the gate (20) with a material having a conductivity substantially opposite a conductivity of the body region (18).

Abstract: Within a damascene method for forming a patterned conductor layer within an aperture defined by a patterned dielectric layer within a microelectronic fabrication, at least one of: (1) the patterned dielectric layer is thermally annealed at a temperature of from about 300 to about 450 degrees centigrade prior to forming within the aperture the patterned conductor layer; and (2) the aperture is etched with a plasma employing an etchant gas composition comprising hydrogen to form a laterally enlarged aperture prior to forming within the laterally enlarged aperture the patterned conductor layer. In accord with the method, the microelectronic fabrication is formed with decreased contact resistance and enhanced structural integrity.

Abstract: The present invention fabricates an oxide-nitride-oxide (ONO) layer of an NROM. A first oxide layer is formed on the surface of the substrate of a semiconductor wafer. Then two CVD processes are performed to respectively form a first nitride layer and a second nitride layer on the surface of the first oxide layer, and the boundary between the second nitride layer and the first nitride layer is so forming an interface. Thereafter, a second oxide layer is formed on the surface of the second nitride layer completing the process of manufacturing the ONO layer. The second nitride layer and the first nitride layer are used as a floating gate of the NROM, and the interface is used as a deep charge trapping center to improve the charge trapping efficiency, and furthermore, to improve the endurance and reliability of the NROM.

Abstract: The present invention provides a method of forming an electroluminescent circuit by screen printing. The method according to the invention includes screen printing a rear electrode pattern on a substrate, which is preferably a polyester sheet, screen printing a dielectric layer over the rear electrode pattern, screen printing a front electrode pattern on the dielectric layer, and screen printing a phosphor layer over the front electrode layer. The rear electrode pattern preferably includes a solid layer disposed upon the substrate and the front electrode pattern preferably includes a plurality of opaque lines separated by spaces. In an alternative embodiment, the method according to the invention includes screen printing the phosphor layer on the substrate, screen printing the front electrode pattern on the phosphor layer, screen printing the dielectric layer over the front electrode pattern, and screen printing the rear electrode pattern over the dielectric layer.

Abstract: The present invention is a film forming method of forming a film of a treatment solution on the front face of a substrate in a treatment chamber including the steps of: supplying the treatment solution to the substrate mounted on a holding member in the treatment chamber in states of gas being supplied into the treatment chamber and of an atmosphere in the treatment chamber being exhausted; and measuring the temperature of the front face of the substrate before the supply of the treatment solution. The measurement of the temperature of the front face of the substrate before the supply of the treatment solution enables the check of the temperature of the front face of the substrate and the temperature distribution. Then, the measured result is compared with a previously obtained ideal temperature distribution for the formation of a film with a uniform thickness, thereby predicting the film thickness of the film which will be formed in the following processing.

Abstract: The present invention concerns the field of microstructures and in particular microstructures made via CMOS technology on semiconductor substrates intended to undergo micro-machining by wet chemical etching, in particular by a KOH etchant. According to the present invention, protection against the KOH reactive agent is provided to such a structure by the deposition of a metal film (40, 41, 43) including at least on external gold layer (43) on the surface of the structure. This metal film (40, 41, 43) advantageously allows the use of mechanical protective equipment to be omitted and thus allows the wafers to be processed in batches. The present invention also proves perfectly compatible with a standard gold bumping process.

Abstract: A method of forming metallic layers on a substrate includes the steps of forming a first layer including a first metal on the substrate; cooling the first layer for a period of time sufficient to suppress formation of an intermetallic phase; and forming a second layer including a second metal distinct from the first metal on the first layer. The cooling step decreases the roughness of the resultant stacked structure by suppressing the formation of an intermetallic phase layer between the two metallic layers and by suppressing “bumps” or other surface irregularities that may form at relatively reactive grain boundaries in the first layer.

Abstract: A method for fabricating a CUB DRAM device having an enlarged process window for bit line contact patterning is deacribed. A plurality of capacitor node contact junctions and a bit line junction are provided in a semiconductor substrate. A node contact plug is formed through a first insulating layer to each of the capacitor node contact junctions. A bit line contact plug is formed to the bit line junction. Openings are etched through a second insulating layer to each of the node contact plugs. A polysilicon layer is conformally deposited within the openings and then recessed below the top of the openings wherein each of the polysilicon layers forms a bottom plate electrode of a capacitor. A capacitor dielectric layer is formed overlying the bottom plate electrodes and the second insulating layer. A polysilicon layer is deposited overlying the capacitor dialectic layer and patterned to form top capacitor plates overlying each of the bottom plate electrodes to complete the capacitors.

Abstract: Methods for reducing contamination of semiconductor substrates after processing are provided. The methods include heating the processed substrate to remove adsorbed chemical species from the substrate surface by thermal desorption. Thermal desorption can be performed either in-situ or ex-situ. The substrate can be heated by convection, conduction, and/or radiant heating. The substrate can also be heated by treating the surface of the processed substrate with an inert plasma during which treatment ions in the plasma bombard the substrate surface raising the temperature thereof. Thermal desorption can also be performed ex-situ by applying thermal energy to the substrate during transport of the substrate from the processing chamber and/or by transporting the substrate to a transport module (e.g., a load lock) or to a second processing chamber for heating. Thermal desorption during transport can be enhanced by purging an inert gas over the substrate surface.

Abstract: A thermal oxide film is formed on a silicon substrate, a polysilicon film is formed on the thermal oxide film, and further a patterned photoresist film is formed on the polysilicon. The polysilicon film and the thermal oxide film are etched using the photoresist film as a mask so as to form a gate electrode and a gate oxide film. The photoresist film is removed therefrom, and a thermal oxide film is formed in the circumference of the gate electrode, thereby to restore a constriction formed in the gate oxide film. A part of the thermal oxide film which corresponds to the gate electrode and another part thereof which corresponds to the semiconductor substrate are removed therefrom, and a side wall nitride film which adhere to the silicon substrate is formed on a side wall of the gate electrode. Thereafter, a source and drain diffusion layers corresponding to the gate electrode are formed on the silicon substrate, thereby to form metal wiring.

Abstract: Metal silicides form low resistance contacts on semiconductor devices such as transistors. Rough interfaces are formed between metal silicide contacts, such as NiSi and the source/drain regions of a transistor, such as doped source/drain regions. Interfaces with a high degree of roughness result in increased spiking and junction leakage. Interface roughness is minimized by deeply doping the source/drain regions of a silicon on insulator substrate.

Abstract: A process for forming a dual damascene opening, in a composite layer comprised with low k layers, to accommodate a dual damascene type, copper structure, has been developed. The process features the use of a silicon oxide layer, formed on the surfaces of the composite layer, exposed in the narrow diameter, via hole component of the dual damascene opening. The silicon oxide layer prevents via poisoning, or outgassing of amines or hydroxyls from the low k layers exposed in the via hole opening, that can evolve during a subsequent photolithographic development cycle, used to define the trench shape component of the dual damascene opening. The protective silicon oxide layer is conformally formed on the exposed-surfaces of the via hole component, via a liquid phase deposition procedure, performed at room temperature.

Abstract: The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass comprises silicon and the second mass comprises silicon oxide. A sacrificial layer is formed over the first mass. While the sacrificial layer is over the first mass, a nitrogen-containing material is formed across the second mass. After the nitrogen-containing material is formed, the sacrificial layer is removed. Subsequently, a silicon nitride layer is formed to extend across the first and second masses, with the silicon nitride layer being over the nitrogen-containing material. Also, a conductivity-enhancing dopant is provided within the first mass. The invention also pertains to methods of forming capacitor constructions.

Abstract: In a method for handling in parallel a plurality of circuit chips, which are arranged in a first arrangement, which corresponds to their arrangement in the original wafer, on the surface of an auxiliary carrier, the plurality of circuit chips is picked up by a plurality of pick up devices. The plurality of pick up devices with the picked up circuit chips is moved simultaneously to one or several carriers, in such a way that, simultaneously with the motion, the first arrangement of the circuit chips is changed into a second arrangement, which is different from the first arrangement. Then the circuit chips are simultaneously placed in the second arrangement on the one or several carriers.

Abstract: A method of manufacturing a semiconductor device includes forming a second barrier layer over a first level, forming a first dielectric layer over the second barrier layer, forming a second dielectric layer over the first dielectric layer, etching the first and second dielectric layers to form an opening through the first dielectric layer and the second dielectric layer, depositing an organic fill material in the opening and removing a portion of the organic fill material before etching the second dielectric layer to form a trench. The organic fill material can then be completely removed and the second barrier layer is etched to expose the first level. The trench and a via are then filled with a conductive material to form a feature.

Abstract: A trench capacitor with an expanded area for use in a memory cell and a method for making the same are provided. The trench capacitor includes a vertical trench formed in a semiconductor, a doping region formed around a low portion of the trench, a collar isolation layer formed on an inner sidewall of an upper portion of the trench, a doped silicon liner layer formed on a surface of the collar isolation layer, wherein the doped silicon liner layer is electrically connected to the doping region, a dielectric layer formed on a surface of the doped silicon liner layer and inner sidewall of the lower portion of the trench, and a doped silicon material formed inside the trench.

Abstract: Methods of forming an interface in a dielectric material to act as an indicator for terminating an etching process, and products produced thereby.

Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device on a first surface of a silicon carbide substrate and with at least one metal contact for the device on the first surface of the substrate. The opposite, second surface of the substrate is then ground and polished until it is substantially transparent. The method then includes masking the polished second surface of the silicon carbide substrate to define a predetermined location for a via that is opposite the device metal contact on the first surface; etching the desired via through the desired masked location until the etch reaches the metal contact on the first surface; and metallizing the via to provide an electrical contact from the second surface of the substrate to the metal contact and to the device on the first surface of the substrate.

Abstract: In pre-treating a surface of a substrate in a process of forming a narrowed thin film pattern on the surface of the substrate from a solution such as a plating liquid, a mask with an opening corresponding to the thin film pattern to be formed later is formed on the surface of the substrate. Then, by micronizing a pre-treating liquid such as a water, a plating liquid, an acidic liquid ad an alkaline liquid, an atmosphere containing microparticles having diameters smaller than the minimum distance of the opening of the mask is produced. The substrate is positioned into the atmosphere, and the microparticles of the pre-treating liquid are stuck on the surface of the substrate exposing to the lower part of the opening of the mask. In using a water as the pre-treating liquid, the substrate is positioned into an atmosphere containing moisture vapor and the water particles are stuck on the surface of the substrate through their condensation.

Abstract: A method of manufacturing a semiconductor device is obtained which is capable of evading generation of a short circuit between wirings in an upper wiring layer even if a part of an upper surface of an FSG film is exposed by variations in a production step. After a USG film (4) is deposited to a thickness of 1 Hm over an entire surface of an FSG film (3), the USG film (4) is polished and removed by a thickness of 900 nm from an upper surface thereof by the CMP method. At this time, part of an upper surface of the FSG film (3) is exposed by variations in a production step. Next, the surface of the interlayer dielectric film (50) is cleaned with a cleaning liquid whose etching rate to the FSG film (3) and etching rate to the USG film (5) are substantially the same. Such a cleaning liquid may be, for example, an ammonia hydrogen peroxide mixture of NH4OH:H2O2:H2O=1:1:20. The structure shown in FIG.