Abstract: A new method of fabricating shallow trench isolations has been achieved. A pad oxide layer is formed overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. A protective layer is deposited overlying the silicon nitride layer. The protective layer, the silicon nitride layer, and the pad oxide layer are patterned to expose the semiconductor substrate where shallow trench isolations are planned. The semiconductor substrate is etched to form trenches for the planned shallow trench isolations. A large trench etching angle is used. The presence of the protective layer prevents loss of the silicon nitride layer during the etching. A trench filling layer is deposited overlying the protective layer and filling the trenches. The trench filling layer and the protective layer are polished down to complete the shallow trench isolations in the manufacture of the integrated circuit device.

Abstract: A method fabricates an integrated semiconductor product. The first step is providing a semiconductor wafer that has preformed semiconductor components. The next step is forming at least one connection, in particular a polysilicon connection. The next step is exposing the at least one connection from the wafer front surface. The next step is applying a protective layer, in particular a silicon nitride protective layer, to the wafer front surface. The next step is treating the wafer front surface by a chemical mechanical polishing (CMP) step, with the result that the at least one connection is made accessible again.

Abstract: The present invention provides a semiconductor device that reduces the junction leak current and achieves an improvement in the reliability of the gate oxide film by minimizing divot formation and the occurrence of a kink and a method of manufacturing such a semiconductor device. A pad oxide film and a silicon nitride film are formed on an Si substrate and a groove-like trench is formed through photolithography and etching. The liner oxide of the trench are oxidized through oxidizing/nitriding. Then, the trench is filled with an insulating film, the insulating film is planarized and the silicon nitride film and the pad oxide film are removed. Next, a field area is formed and a transistor is formed by following specific steps. By forming a trench liner oxide film containing nitrogen, stress is reduced.

Abstract: A method comprising forming as stacked materials on a substrate, a volume of programmable material and a signal line, conformably forming a first dielectric material on the stacked materials, forming a second dielectric material on the first material, etching an opening in the second dielectric material with an etchant that, between the first dielectric material and the second dielectric material, favors removal of the second dielectric material, and forming a contact in the opening to the stacked materials. An apparatus comprising a contact point formed on a substrate, a volume of programmable material formed on the contact point, a signal line formed on the volume of programmable material, a first dielectric material conformally formed on the signal line, a different second dielectric material formed on the first dielectric material, and a contact formed through the first dielectric material and the second dielectric material to the signal line.

Abstract: A method of manufacturing a bipolar transistor in a single-crystal silicon substrate of a first conductivity type, including a step of carbon implantation at the substrate surface followed by an anneal step, before forming, by epitaxy, the transistor base in the form of a single-crystal semiconductor multilayer including at least a lower layer, a heavily-doped median layer of the second conductivity type, and an upper layer that contacts a heavily-doped emitter of the first conductivity type.

Abstract: A new method is provided that allows placing or stacking staggered bond I/O buffers into linear bond I/O buffers. The bond pads are linearly arranged, the interface between the staggered bond pad I/O buffers and the linearly arranged bond pads is achieved by a frame design that sequentially connects the staggered bond pad I/O buffers to the linearly arranged bond pads.

Abstract: A method of filling a contact hole of a semiconductor device preceded by dry cleaning for removing a damaged layer resulting from dry etching is provided. The method includes selectively exposing an underlying material layer by a dry etch and dry cleaning including passing plasma excited from a source gas over the exposed underlying material layer to remove the damaged layer formed from the dry etch. Subsequently, an electrically conductive layer with which to fill the contact hole is formed. The formation of the electrically conductive layer is performed in a separate chamber connected sequentially to a chamber for performing the dry cleaning to prevent the exposed underlying material layer inside the dry cleaned contact hole from being exposed to a source of contamination.

Abstract: A non-volatile memory cell includes a MOS transistor having a ring arrangement and comprising a floating gate, a center electrode at a center of the ring arrangement and surrounding the floating gate, and at least one peripheral electrode along a periphery of the ring arrangement.

Abstract: A method of forming a carbon-doped silicon oxide layer is disclosed. The carbon-doped silicon oxide layer is formed by applying an electric field to a gas mixture comprising an organosilane compound and an oxidizing gas. The carbon-doped silicon oxide layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the carbon-doped silicon oxide layer is used as an intermetal dielectric layer. In another integrated circuit fabrication process, the carbon-doped silicon oxide layer is incorporated into a damascene structure.

Abstract: The present invention discloses the new structure with regard to a nonvolatile semiconductor memory which can store therein an information corresponding to a plurality of bits. The nonvolatile semiconductor memory according to the present invention has a charge trapping layer 4 for accumulating electrons, in an end of a gate electrode. In the nonvolatile semiconductor memory according to the present invention, the electrons are stored in this charge trapping layer 4 to thereby store the information corresponding to the plurality of bits.

Abstract: A method of fabricating a sub-micron MOS transistor includes preparing a substrate, including isolating an active region therein; depositing a gate oxide layer; depositing a first selective etchable layer over the gate oxide layer; depositing a second selective etchable layer over the first selective etchable layer; etching the structure to undercut the first selective etchable layer; implanting ions in the active region to form a source region and a drain region; depositing and planarizing the oxide; removing the remaining first selective etchable layer and the second selective etchable layer; depositing a gate electrode; and depositing oxide and metallizing the structure. A sub-micron MOS transistor includes a substrate; and an active region, including a gate region having a length of less than one micron; a source region including a LDD source region; and a drain region including a LDD drain region.

Abstract: A method for making CMOQ transistors and associated devices. The method is used to make transistors of a first type and a second type in CMOS technology in an active layer. The method etches regions of the active layer or making them inactive so as to define active islands designed to form sources, channels of determined width, and drains of the transistors of the first type and second type respectively, covers at least two active islands with an insulating layer and covers the insulating layer with a conductive layer, and sequentially etches all the gates of the transistors of the first type and then all the gates of the transistors of the second type. The associated devices includes CMOS transistor devices obtained by the method. Such a method may particularly find application to devices for the addressing and control of active matrix liquid crystal displays.

Abstract: A semiconductor memory and its manufacturing method enable high-integrated memory cell to be realized easily. The semiconductor memory according to the present invention has an impurity diffusion region with a second conductive type that is opposite to a first conductive type on a surface of a semiconductor substrate with the first conductive type. Further, the semiconductor memory has structure in which there are provided a floating gate electrode formed on the semiconductor substrate via a gate insulator, and a control gate electrode formed on the floating gate electrode via an interelectrode insulating film. Furthermore, there are provided the gate insulator on the surface of the semiconductor substrate with the exception of an impurity diffusion region, and a third insulating film with film thickness thicker than that of the gate insulator on the surface of the impurity diffusion region.

Abstract: A composition for removing side wall which includes an aqueous solution containing both nitric acid and at least one of carboxylic acids selected from the group consisting of polycarboxylic acid, aminocarboxylic acid, and salts thereof; a method of removing side wall; and a process for producing a semiconductor device. Use of the composition is effective in removing side wall at a low temperature in a short time in semiconductor device production without corroding the wiring material, e.g., an aluminium alloy. Thus, a semiconductor device having an aluminium alloy wiring which has undergone substantially no corrosion can be efficiently produced.

Abstract: A method is used to form an insulating layer with foamed structure. About the method, a gel layer over a substrate, where the gel layer includes several types of solution, an unextractable material, and a solvent. The substrate is then put in a closed pressure chamber. The closed pressure chamber is heated to a subcritical temperature with respect to the material which is included in the gel layer but to be extracted out. In this situation, liquid and the material to be extracted all turn to a vapor phase due to the pressure in the pressure chamber has reached the subcritical pressure, whereby materials are extracted. Under this temperature, the vapor is flushed away, and a noble gas is flushed into the pressure chamber for cleaning. The substrate with the gel layer is cooled down to the environmental temperature. Then the substrate is taken out from the pressure chamber.

Abstract: A method for processing substrates, in which a photoresist layer is applied and structured on their surface. By blasting the substrate with particles, recesses are put into the surface of the substrate in those areas not covered by photoresist.

Abstract: In a semiconductor device having a fuse and an etching stopper film covering the fuse, an optical window exposing the etching stopper film and a contact hole exposing a conductor pattern are formed simultaneously. By applying a dry etching process further to the etching stopper film, an insulation film covering the fuse is exposed in the optical window.

Abstract: A barrier metal that can be used in a semiconductor is to be made extremely thin. Further, the manufacturing steps of a semiconductor device are shortened to reduce its manufacturing cost. An insulating layer (e.g., a thermal nitride layer 10) with good step coverage formed on a surface of a conductor film such as lower electrodes 9 and 9a of a capacitor on a semiconductor substrate is transformed into a reformed layer 11, which serves as a conductive barrier layer. Alternatively, the insulating layer formed on the surface of the insulating layer on the semiconductor substrate is totally or partially reformed into the conductive barrier layer. This reforming process is conducted by heating the above-mentioned semiconductor substrate at a predetermined temperature and, applying a plasma-excited high melting-point metal onto the surface of the above-mentioned insulating layer. This high melting-point metal may be Ti, Ta, Ni, Mo, W or the like.

Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the polycrystalline first silicon layer has a positive in temperature dependence of resist while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

Abstract: A micro-electromechanical (MEM) process for fabrication of integrated multi-frequency communication passive components is fused into co-fired ceramics by way of “flip chip” for fabrication of a low-cost, high-performance, and high-reliability hybrid communication passive component applicable in the frequency range of 0.9 GHz˜100 GHz. The basic structure of the passive component is a double-layer substrate comprising a low-loss ceramic or glass bottom-layer substrate and a glass or plastic poly-molecular top-layer substrate and an optional ceramic substrate at the lowest layer. As the materials used and the processing temperature in the MEM process is compatible with the CMOS process, thus this invention is fit for serving as a post process following the CMOS process.