Abstract: A method and apparatus for fabricating silica-based waveguide devices on a substrate using a low temperature PECVD process using a TEOS source material for depositing waveguide layers containing silica, the apparatus being arranged, in use, in a manner such that a liquid source material containing silicon is used during the PECVD.

Abstract: A deep submicron MOS transistor is formed with multiple control gates by forming side wall control gates adjacent to the gate oxide spacers over heavily-doped regions of the source and drain regions. The side wall control gates can be used to substantially increase the threshold voltage of the transistor.

Abstract: A method for operating a P-channel SONOS memory device that has a charge trapping layer located on a substrate, a gate electrode located on the trapping layer, two doped regions located in the substrate at each side of the charge trapping layer. The two doped regions are set to be a drain region and a source region. When a programming action is intended, the gate electrode and the drain region are applied with a first negative high-level bias, and the source region and the substrate are applied with a grounded voltage. When an erasing action is intended, the gate electrode is a second negative bias which is smaller than the first negative voltage in absolute value. In the mean time, the drain region is applied with the third negative bias and the substrate is applied with a grounded voltage. The third negative voltage is larger than the second negative bias in absolute value.

Abstract: A method for fabricating a shallow trench isolation structure includes forming a hard mask layer over a substrate. An ion bombardment step is further performed on the surface of the hard mask layer, followed by forming a patterned photoresist layer on the surface of the hard mask layer. Thereafter, the hard mask layer is patterned using the photoresist layer as an etching mask. An etching process is further performed to form a trench in the substrate. The photoresist layer is then removed, followed by filling an insulation layer in the trench. After this, the hard mask is removed to complete the fabrication of a shallow trench isolation region.

Abstract: The wet etch stage of the salicide process normally used to fabricate polysilicon and silicon-based semiconductor transistors may not be appropriate for germanium-based transistors because the wet etch chemicals at such temperatures will dissolve the germanium leaving no source, gate, or drain for the transistor. In embodiments of the invention, nickel is blanket deposited over the source, drain, and gate regions of the germanium-based transistor, annealed to cause the nickel to react with the germanium, and wet etched to remove un-reacted nickel from dielectric regions (e.g., shallow trench isolation (STI) regions) but leave NiGe in the source, gate, and drain regions. The wet etch is a mild oxidizing solution at room temperature.

Abstract: A method of planarizing an image sensor substrate is disclosed. The method comprises depositing a first polymer layer over the image sensor substrate. The first polymer layer is patterned to form pillars. Then, a second polymer layer is deposited over the pillars. Optionally, the second polymer layer is etched back.

Abstract: The novel trench capacitors have a constant or increased capacitance. Materials for a second electrode region and if appropriate a first electrode region include a metallic material, a metal nitride, or the like, and/or a dielectric region is formed with a material with an increased dielectric constant. An insulation region is formed in the upper wall region of the trench after the first electrode region or the second electrode region has been formed, by selective and local oxidation.

Abstract: A capacitor having improved size for enhanced capacitance and a method of forming the same are disclosed. In one embodiment, the capacitor is a stacked container capacitor used in a dynamic random access memory circuit. The capacitor provides a capacitor that has high storage capacitance which provides an increased efficiency for a cell without an increase in the size of the cell.

Abstract: The proposed invention is related to a method for forming a gate with metal silicide. In short, the proposed method comprises the following steps: providing a substrate; forming a first dielectric layer on the substrate; forming a polysilicon layer on the first dielectric layer; forming a metal silicide layer on the polysilicon layer; forming a second dielectric layer on the metal silicide layer; etching the second dielectric layer, the metal silicide layer, the polysilicon layer and the first dielectric layer to form a gate; performing a thermal nitridation process to form a metal nitride layer on the sidewall of the metal silicide layer; and performing a thermal oxidation process to eliminate edge defects.

Abstract: A method for forming a fuse pattern for repairing a bad cell includes forming a metal wiring pattern on a substrate and successively forming an insulating layer on the metal wiring pattern and the substrate. The insulating layer of a region for defining the fuse pattern is etched by using an etching gas including a fluorocarbon-type compound and a fluorosilicate-type compound, which substantially suppresses a generation of by-products. A partially exposed metal layer of the metal wiring pattern is removed to form a fuse. Accordingly, a structure such as a fence is not formed on the residue of insulating layer. Therefore, the removal process for the fence is unnecessary. As a result, the process for forming the fuse is simplified.

Abstract: A semiconductor structure includes a dielectric layer having first and second opposing sides. A conductive layer is adjacent to the first side of the dielectric layer and is coupled to a first terminal, and a conductive barrier layer is adjacent to the second side of the dielectric layer and is coupled to a second terminal. The conductive barrier layer may be formed from tungsten nitride, tungsten silicon nitride, titanium silicon nitride or other barrier material.

Abstract: The invention provides a general fabrication method for producing MicroElectroMechanical Systems (MEMS) and related devices using Silicon-On-Insulator (SOI). One first obtains an SOI wafer that has (i) a handle layer, (ii) a a dielectric layer, and (iii) a device layer. A mesa etch has been made on the device layer of the SOI wafer and a structural etch has been made on the dielectric layer of the SOI wafer. One then obtains a substrate (such as glass or silicon), where a pattern has been etched onto the substrate. The SOI wafer and the substrate are bonded together. Then the handle layer of the SOI wafer is removed, followed by the dielectric layer of the SOI wafer.

Abstract: A device (1,21,28, 36, 37, 86, 103, 121, 128) for electronic packaging, the device including a discrete solid body having a pair of opposing generally parallel major surfaces, the solid body having a body portion of a porous valve metal oxide based material with a pair of exterior surfaces respectively constituting portions of the major surfaces and extending inward from one major surface towards the other major surface, the body portion having one or more electrically insulated valve metal conductive traces of from about 10 &mgr;m to about 400 &mgr;m thickness in a direction from one major surface to the other major surface embedded therein, one or more of said traces having a trace portion divergingly extending inward from an exterior surface constituting a portion of one of said major surfaces.

Abstract: In a semiconductor device having a built-in contact-type sensor, a height of a surrounding part of a sensor part from the exposed surface of the sensor part is reduced. The semiconductor device has a semiconductor element having a built-in sensor. The semiconductor element has a circuit forming surface and a back surface opposite to the circuit forming surface. The contact-type sensor and electrodes are formed on the circuit forming surface. Back electrodes are formed on the back surface. Conductive members extend through the semiconductor device from the electrodes to the back electrodes. A protective film covers the circuit forming surface in a state where the surface of the contact-type sensor is exposed. External connection terminals are electrically connected to the back electrodes.

Abstract: A platen for electrostatic wafer clamping apparatus comprising a platen body of dielectric material and grains of electrically conductive material diffused in the dielectric material so that the platen has a relatively large electrostatic capacitance due to the diffusion of the conductive grains with the result that the platen provides an increased clamping force regardless of humidity. In accordance with another aspect of the invention, the thickness of the platen body can be decreased by an amount sufficient to maintain a constant clamping force with reduced applied voltage, to eliminate any residual voltage on the platen and to increase the speed of wafer release. The grains of electrically conductive material are present in an amount of from about 2.5 percent to about 15.0 percent of the volume of the platen body, and the grains of electrically conductive material are selected from the group consisting of carbonated transition metals, nitrified transition metals and carbonated grains.

Abstract: A method for fabricating a semiconductor package is performed using a mold tooling fixture having a mold cavity and a pair of flash control cavities on either side of the mold cavity. The semiconductor package includes a substrate and a semiconductor die attached to the substrate. The substrate includes a pattern of conductors wire bonded to the die, and an array of solder balls bonded to ball bonding pads on the conductors. In addition, the substrate includes a die encapsulant encapsulating the die, and a wire bond encapsulant encapsulating the wire bonds. During molding of the wire bond encapsulant, the flash control cavities collect flash, and provide pressure relief for venting the mold cavity. In addition, the flash control cavities restrict the flash to a selected area of the package substrate, such that the ball bonding pads and solder balls are not contaminated.

Abstract: A device and manufacturing method for a semiconductor device includes the steps of forming a penetration hole 50 in a semiconductor chip 10 having an electrode 14, and forming a conductive layer 70 in the region including the inside of the penetration hole 50. Regarding the penetration hole 50, an intermediate portion is formed to be larger than an open end portion, and the conductive layer 70 is formed by applying a coating of a liquid containing metal fine particles by an ink-jet method.

Abstract: Disclosed is a semiconductor device manufacturing apparatus provided with a rotational gas injector for supplying source gases at an upper portion of a reaction chamber. According to the invention, source gases are injected from the upside of the wafers through the rotational type gas injector, and non-reacted gases are exhausted into the downside space of the wafers, so that lowering in the thickness uniformity of a thin film due to the horizontal flow of source gases provided in the conventional art decrease remarkably. Accordingly, although multiple wafers are loaded in a single reaction chamber, a thin film having very high thickness uniformity can be deposited with respect to all the wafers, thereby capable of enhancing the productivity.

Abstract: There is provided a patterning method which makes it possible to form a desired preferable pattern having no reduction in the pattern thickness in a boundary portion where a group of patterns are joined using a plurality of exposure masks. There is provided a patterning method for forming a group of patterns in which first patterns to serve as basic units are repetitively arranged using a plurality of exposure masks. When a third region sandwiched by a first region exposed with a first exposure mask and a second region exposed with a second exposure mask is exposed with the first and second exposure masks in a complementary manner, repetitive unit patterns for exposing the third region are different from the first patterns.

Abstract: The present invention concerns the field of microstructures and in particular microstructures made via CMOS technology on semiconductor substrates intended to undergo micro-machining by wet chemical etching, in particular by a KOH etchant. According to the present invention, protection against the KOH reactive agent is provided to such a structure by the deposition of a metal film (40, 41, 43) including at least on external gold layer (43) on the surface of the structure. This metal film (40, 41, 43) advantageously allows the use of mechanical protective equipment to be omitted and thus allows the wafers to be processed in batches. The present invention also proves perfectly compatible with a standard gold bumping process.