Abstract: A memory device includes a first data driver configured to send a first data according to a first clock signal; a first data port electrically coupled to the first data driver, the first data port configured to receive the first data; a second data driver configured to send a second data according to a second clock signal, wherein the second clock signal does not match the first clock signal; and a second data port electrically coupled to the second data driver, the second data port configured to receive the second data.

Abstract: A memory apparatus includes a memory cell array including a plurality of memory cells, a temperature sensor, a temperature compensated self refresh (TCSR) block, and a command controller. The temperature sensor is configured to generate temperature information by measuring internal temperature of the memory apparatus. The TCSR block is configured to vary and output, in a test mode of the memory apparatus, period information for adjusting a refresh period for the memory cell array according to the temperature information. The command controller is configured to adjust, in response to the period information, the refresh period for the memory cell array by controlling an external command.

Abstract: A crossbar array includes a number of memory elements. A vector input register has N voltage inputs to the crossbar array. A vector output register has M voltage outputs from the crossbar array. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A clustering processor is electronically coupled to the ADC and to the DAC. The clustering processor is configured to program columns of the crossbar array with a set of k cluster center values; apply voltages to rows of the crossbar array where the applied voltages represent a set of data values; and determine a minimum distance of each data value to each k cluster center values based on the voltage output from the output register of each of the plurality of the programmed columns.

Abstract: Systems include a first semiconductor die comprising a charge pump to generate power supply signals, a second semiconductor die comprising a memory array and programming circuitry, and a bus connected to the first and second semiconductor dies to carry the power supply signals to the programming circuitry. The programming circuitry is adapted to program memory cells of the memory array to respective threshold voltages that are each less than or equal to the first voltage.

Abstract: A computer-implemented method for remediating disruptions to memory cells is described. The method includes writing user data to an aggressor memory cell and determining one or more of a write timestamp and an overwrite count associated with the aggressor memory cell. The write timestamp indicates a last write to the aggressor memory cell and the overwrite count indicates the number of writes to the aggressor memory cell during a time period. Based on one or more of the write timestamp and the overwrite count, an increment value is determined for use with a disturb counter associated with a neighbor memory cell of the aggressor memory cell. In particular, the determined increment value is used, in response to the write, to increment the disturb counter associated with the neighbor memory cell. When the disturb counter is greater than or equal to a disturb threshold, remediation for the neighbor memory cell is performed.

Abstract: A first memory section is disposed on a substrate. A second memory section is vertically stacked on the first memory section. The first memory section is provided between the substrate and the second memory section. The first memory section includes a flash memory cell structure, and the second memory section includes a variable resistance memory cell structure. The flash memory cell structure includes at least one cell string comprising a plurality of first memory cells connected in series to each other and a bit line on the substrate connected to the at least one cell string. The bit line is interposed vertically between the at least one cell string and the second memory section and connected to the second memory section.

Abstract: According to one embodiment, a memory device is connectable to a host, and includes a nonvolatile memory, a volatile memory which is used as a cache of the nonvolatile memory and has a higher access speed than the nonvolatile memory, and a controller which controls access to the nonvolatile memory and the volatile memory. The controller increments, when the controller receives a refresh command for the volatile memory from the host, a value of a refresh counter, and executes, when the value of the refresh counter exceeds a threshold, no refresh operation corresponding to the refresh command.

Abstract: A memory system is connectable to a host and comprises a memory chip including a nonvolatile semiconductor memory cell array, a memory controller, a first temperature sensor positioned to measure a first temperature, which is representative of a temperature of the memory controller, and a second temperature sensor positioned to measure a second temperature, which is representative of a temperature of the memory chip. The memory controller is configured to compare the first temperature against a first threshold temperature and a second temperature against a second threshold temperature and carry out access to the memory chip when either the first temperature is greater than the first threshold temperature or the second temperature is greater than the second threshold temperature.

Abstract: Apparatuses and techniques are described for programming phase change memory cells while avoiding a clamp condition in transistors which are used for biasing a word line and bit line when the word line and bit line are unselected for a write operation. The transistors may be connected in parallel with the word line and bit line. During a write operation, a current source is connected to a selected word line and a voltage control circuit is connected to the selected bit line. The voltage control circuit can include a capacitor or a voltage driver, for example. The capacitor accumulates charge, or the voltage driver applies an increasing ramp voltage to the bit line, to increase the voltage of the bit line and word line during the write operation and to avoid the clamp condition.

Abstract: The present disclosure provides DNA-based storage system demonstrated through experimental and theoretical verification that such a platform can easily be implemented in practice using portable, nanopore-based sequencers. The gist of the approach is to design an integrated pipeline that encodes data to avoid synthesis and sequencing errors, enables random access through addressing, and leverages efficient portable nanopore sequencing via new anchored iterative alignment and insertion/deletion error-correcting codes. The embodiments herein represent the only known random access DNA-based data storage system that uses error-prone portable, nanopore-based sequencers and produces low-error readouts with the highest reported information rate and density.

Abstract: Apparatus, systems, methods, and computer program products for adaptive power balancing in memory device operations are disclosed. One apparatus includes a power balancing component for the memory device. A power balancing component is configured to determine a first amount of power consumed by each respective operation in a set of operations for a memory device for at least one previous iteration of each respective operation. A power balancing component utilizes a second amount of power to perform a next iteration of each respective operation based on a first amount of power consumed by each respective operation in at least one previous iteration.

Abstract: Semiconductor memory testing devices and methods are disclosed. In one respect, a device is disclosed that includes a first memory cell array having a first bit-line and a plurality of first memory cells coupled to the first bit-line; a second memory cell array having a second bit-line and a plurality of second memory cells coupled to the second bit-line, the number of second memory cells being smaller than that of the first memory cells; a sense amplifier coupled to the first bit-line and a first end of the second bit-line; a word decoder configured to operate the second memory cells responsive to a first test signal; and a transistor coupled to a second end of the second bit-line and operated by a second test signal.

Abstract: Memory systems can include shifting an ODT information signal prior to passing it through a cloned DLL delay line. The shifted ODT information passes through a cloned DLL delay line to move it into a DLL domain. Meanwhile, a clock gate can use a command indication to select whether to provide a clock signal to a DLL delay line. The clock gate can block the clock signal in the absence of a read or write operation and can pass the clock signal during read or write operations. When the DLL delay line receives the clock signal, it delays the clock signal to be in the DLL domain. By locating the ODT shifter before the cloned DLL delay line, as opposed to after it, the ODT shifter doesn't need a signal passed through the DLL delay line. Preventing the clock signal from passing through the DLL delay line reduces power consumption.

Abstract: Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.

Abstract: A semiconductor memory device includes memory cell arrays that include a plurality of memory cells. A first control circuit with control transistors of a first conductivity type is in a first region below the memory cell arrays. A second control circuit includes a first transistor of a first conductivity type connected in parallel to a second transistor of a second conductivity type. One of the first and second transistors is connected to an end of at least one control transistor. The second control circuit delivers a voltage to the plurality of control transistors. The first transistor is disposed in the first region. The second transistor is disposed in a second region adjacent to the first region. The second region is below a gap between adjacent memory cell arrays.

Abstract: A semiconductor memory device includes a memory core that performs reading and writing of data, data delivery and training blocks that are connected between first pads and the memory core, and at least one data delivery, clock generation and training block that is connected between at least one second pad and the memory core. In a first training operation, the data delivery and training blocks output first training data, received through the first pads, through the first pads as second training data. In a second training operation, at least one of the data delivery and training blocks outputs third training data, received through the at least one second pad, through at least one of the first pads as fourth training data. The second training data and the fourth training data are output in synchronization with read data strobe signals output through the at least one second pad.

Abstract: According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.

Abstract: Methods, systems, and apparatus, including medium-encoded computer program products, for analyzing data include: receiving data including responses, and lack thereof, for items of a cognitive test including multiple item-recall trials; processing the data using a stochastic model of a cognitive process, in which a conditional probability distribution of future states of the cognitive process depend upon a present state; and encoding a result of the processing on a non-transitory computer-readable medium for use in an assessment related to cognition; wherein the processing using the stochastic model includes representing recall or recognition of an item in the multiple item-recall trials using distinct cognitive states; and wherein the processing using the stochastic model includes adjusting separate memory storage and retrieval parameters for each of the distinct cognitive states in the modeled cognitive process to account for position of the items in each respective trial of the multiple item-recall trials.

Abstract: Certain apparatuses, systems, methods, and computer program products are used for multi-plane memory management. An apparatus includes a failure detection circuit that detects a failure of a storage element during an operation. An apparatus includes a test circuit that performs a test on a storage element. An apparatus includes a recycle circuit that enables a portion of a storage element for use in operations in response to the portion of the storage element passing a test.

Abstract: A method and apparatus for ply blending. A desired thickness and a desired stiffness distribution for a composite structure are received. A model of the composite structure is split into a plurality of panels. Lamination parameters and a quantity of plies for each panel of the plurality of panels are determined using the desired thickness and the desired stiffness distribution for the composite structure. Ply shapes for each ply of the plurality of panels are determined using an objective function. A fiber angle is determined for each ply of the plurality of panels. Each ply of a first half of a panel of the plurality of panels has a different fiber angle value than each other ply of the first half of the panel.