Abstract: Embodiments of the disclosure provide a method, apparatus, and computer readable medium for optimizing memory card performance.

Abstract: Methods, systems, and devices for memory array operation are described. A series of pulses may be applied to a fatigued memory cell to improve performance of memory cell. For example, a ferroelectric memory cell may enter a fatigue state after a number of access operations are performed at an access rate. After the number of access operations have been performed at the access rate, a fatigue state of the ferroelectric memory cell may be identified and the series of pulses may be applied to the ferroelectric capacitor at a different (e.g., higher) rate. For instance, a delay between pulses of the series of pulses may be shorter than the delay between access operations of the ferroelectric memory cell.

Abstract: A clocked driver circuit can include a level shifter latch and a driver. The level shifter latch can be configured to receive an input signal upon a clock signal and generate a level shifted output signal. The driver can be configured to receive the level shifted output signal from the level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal.

Abstract: A flash memory controller is suitable for a NAND flash memory and a voltage supply circuit. The voltage supply circuit supplies a current to the flash memory. The flash memory controller includes a flash control circuit, a current sensing circuit, and a processor. The flash control circuit is configured to control an operation of the flash memory. The current sensing circuit is configured to measure the current consumed by the flash memory during its operation, and output a current value. The processor is configured to output a control signal based on the current value. Therefore, the flash memory controller can instantly obtain a current value consumed during the operation of flash memory, and determine, based on the current value, whether the flash memory runs normally. A storage apparatus having the flash memory controller can instantly determine whether the flash memory runs normally.

Abstract: According to one embodiment, a memory device is connectable to a host, and includes a nonvolatile memory, a volatile memory which is used as a cache of the nonvolatile memory and has a higher access speed than the nonvolatile memory, and a controller which controls access to the nonvolatile memory and the volatile memory. The controller increments, when the controller receives a refresh command for the volatile memory from the host, a value of a refresh counter, and executes, when the value of the refresh counter exceeds a threshold, no refresh operation corresponding to the refresh command.

Abstract: A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least one super block of the flash memory chips; and allocating a buffer memory space to store a plurality of temporary parities generated when data is written into the at least one first super block.

Abstract: Techniques for fast programming and read operations for memory cells. A first set of bit lines is connected to a first set of NAND strings and is interleaved with a second set of bit lines connected to a second set of NAND strings. The first set of NAND strings can be programmed by driving a voltage on the first set of bit lines while floating a voltage on the second set of bit lines, to reduce an inter-bit line capacitance and provide a relatively high access speed and a relatively low storage density (e.g., bits per memory cell). The second set of NAND strings can be programmed by concurrently driving a voltage on the first and second sets of bit lines, to provide a relatively low access speed and a relatively high storage density.

Abstract: A data readout apparatus may include a comparison circuit structured to compare a pixel signal with the ramp signal to generate a comparison result, a counter array structured to receive the comparison results to count up with each clock pulse from a first timing until a second timing to convert a counted number of clock pulses into differential data and output the differential data through differential data lines, and a sense amplifier array structured to receive the differential data to sense and amplify the differential data based on a judge clock. The sense amplifier array can include a replica delay structured to delay the judge clock and the precharge pulse signal based on a read out timing and read out the data from the counter array at the read out timing.

Abstract: Examples disclosed herein relate, in one aspect, to a method for searching an array of content addressable memory (CAM) devices, where each device stores a plurality of entries. The method may obtain a search key from a processor, search a first set of CAM devices in the array to determine whether the first set of CAM devices include a matching entry corresponding to the search key; upon a determination that the first set of CAM devices does not include the matching entry, search a second set of CAM devices in the array to determine whether the second set of CAM devices include the matching entry; and upon a determination that the first set of CAM devices include the matching entry, output an address of the matching entry, without searching the second set of CAM devices.

Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

Abstract: An information provision apparatus whereby information regarding a malfunction or problem that occurred during the use of a prescribed model of home appliance can be shared with users using the same model of home appliance. A device (20) has the following: a presentation-information reception unit (21) that receives presentation information generated by a server (10) and stores the presentation information in a prescribed storage unit; and a presentation unit (22) that presents the presentation information to the user of the device (20), the presentation information having been read out from the aforementioned storage unit. The presentation information indicates malfunctions or problems that occurred in devices that are the same model as the abovementioned device (20) and were being used by other users.

Abstract: Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a cascode may couple a precharged capacitor with the memory cell to transfer a charge between the precharged capacitor and the memory cell. The cascode may isolate the capacitor from the memory cell based on the charge transferred between the capacitor and the memory cell. A second capacitor (e.g., a parasitic capacitor) may continue to provide an additional amount of charge to the memory cell during the read operation. Such a change in capacitance value during the read operation may provide a large sense window due to a non-linear voltage characteristics associated with the change in capacitance value.

Abstract: Provided herein may be a memory system and a method of operating the memory system. The memory system may include: a nonvolatile memory device configured to perform internal operations in response to command/address sequences; and a memory controller configured to provide the command/address sequences to the nonvolatile memory device. The memory controller may include: a firmware section configured to manage read/write characteristic information about the nonvolatile memory device; and a hardware section configured to generate command/address sequences based on the read/write characteristic information.

Abstract: Semiconductor memory devices and methods of operating the same are provided. The method of operation may include the steps of selecting a ferroelectric memory cell for a read operation, coupling a first pulse signal to interrogate the selected ferroelectric memory cell, the selected ferroelectric memory cell outputting a memory signal to a bit-line in response to the first pulse signal, coupling the memory signal to a first input of a sense amplifier via the bit-line, electrically isolating the sense amplifier from the selected ferroelectric memory cell, and enabling the sense amplifier for sensing after the sense amplifier is electrically isolated from the selected ferroelectric memory cell. Other embodiments are also disclosed.

Abstract: A data reading error is reduced. A memory cell array in a storage device includes a write word line, a read word line, a write bit line, a read bit line, a source line, and a gain cell. For example, a read transistor in the gain cell can include a metal oxide in a channel formation region. A cancel circuit is electrically connected to the read bit line. The cancel circuit has a function of supplying, to the read bit line, current for canceling leakage current supplied to the read bit line from the gain cell in a non-selected state. In read operation, a potential change of the read bit line due to leakage current is compensated for by the current from the cancel circuit, so that a data reading error is reduced.

Abstract: Methods, systems, and apparatuses related to memory operation with common clock signals are provided. A memory device or system that includes one or more memory devices may be operable with a common clock signal without a delay from switching on-die termination on or off. For example, a memory device may comprise first impedance adjustment circuitry configured to provide a first impedance to a received clock signal having a clock impedance and second impedance adjustment circuitry configured to provide a second impedance to the received clock signal. The first impedance and the second impedance may be configured to provide a combined impedance about equal to the clock impedance when the first impedance adjustment circuitry and the second impedance adjustment circuitry are connected to the received clock signal in parallel.

Abstract: A method for accessing a plurality of DRAM devices each having a plurality of banks, the plurality of DRAM devices being interconnected to receive common address and command signals. The method includes receiving a first chip selection address and a first bank address with an active command to activate a first bank in a first DRAM device of the plurality of DRAM devices. A first bank active flag is set, corresponding to the first bank address, in the first DRAM device of the plurality of DRAM devices. A second bank address with a column command is received. A second bank is accessed in a second DRAM device of the plurality of DRAM devices having a set bank active flag corresponding to the second bank address.

Abstract: At least one latch of a page buffer of a nonvolatile memory device includes a capacitor that selectively stores a voltage of a sensing node. The capacitor includes at least one first contact having a second height corresponding to a first height of each of cell strings, and at least one second contact to which a ground voltage is supplied. The at least one second contact has a third height corresponding to the first height, disposed adjacent to the at least one first contact, and electrically separated from the at least one first contact.

Abstract: A data line control circuit has a data line driving circuit and a write-assist data line driving circuit. The data line driving circuit is used to drive differential data lines during a write operation of at least one memory cell. The write-assist data line driving circuit is used to drive at least one write-assist data line during the write operation of the at least one memory cell, wherein the at least one write-assist data line is isolated from the differential data lines, and is driven to have a first voltage transition from a first voltage level to a second voltage level, such that one of the differential data lines has a second voltage transition from a third voltage level to a fourth voltage level that is induced by the first voltage transition via capacitive coupling.

Abstract: A program circuit may two-dimensionally program data into cells by applying different selected bit line or channel voltages to different bit lines or channels located in different bit line zones of a block during a program operation. The block may be further separated or divided into word line zones. The program circuit may adjust the different bit line or channel voltages as it programs in different word line zones of the block. In accordance with the two-dimensional programming, the program circuit may perform single-pulse program-only SLC program operations.