Abstract: The various implementations described herein include methods, devices, and systems for performing operations on memory devices. In one aspect, a memory device includes: (1) a magnetic memory component; and (2) a current selector component coupled to the magnetic memory component, the current selector component including: (a) a first transistor having a first gate with a corresponding first threshold voltage; and (b) a second transistor having a second gate with a corresponding second threshold voltage, distinct from the first threshold voltage; where the second transistor is coupled in parallel with the first transistor.

Abstract: A method for reading a data of a memory cell comprising a selection device and a resistive memory device which has a high resistance state or a low resistance state according to a data stored therein includes: applying a first read voltage to the memory cell; applying a second read voltage to the memory cell, the second read voltage having a level lower than a level of the first read voltage; and sensing the data of the memory cell while the second read voltage is applied to the memory cell.

Abstract: Systems, apparatuses and methods may provide for initiating an erase of a block of non-volatile memory in response to an erase command, wherein the block includes a plurality of sub-blocks. Additionally, a failure of the erase with respect to a first subset of the plurality of sub-blocks may be tracked on an individual sub-block basis, wherein the erase is successful with respect to a second subset of the plurality of sub-blocks. In one example, use of the second subset of the plurality of sub-blocks is permitted, whereas use of the first subset of the plurality of sub-blocks is prevented.

Abstract: A color measurement device includes a measurement array (MA) which includes: a plurality of illumination arrays (20, 30, 40) for exposing a measurement spot (MS) on a measurement object (MO) to illumination light in an actual illumination direction (2, 3, 4) in each case, and a pick-up array (50) for detecting the measurement light reflected by the measurement spot (MS) in an actual observation direction (5) and for converting it into preferably spectral reflection factors; and a controller for the illumination arrays and the pick-up array and for processing the electrical signals produced by the pick-up array. The controller is embodied to process the measured reflection factors on the basis of a correction model, such that distortions in the measurement values as compared to nominal illumination and/or observation directions, caused by angular errors in the illumination arrays and/or the pick-up array, are corrected.

Abstract: In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.

Abstract: A method for accelerating the decision making process for reservoir risk management is described. In particular, an ensemble based decisions and filter are used to quickly compare different information scenarios to determine the best strategy for developing a hydrocarbon-containing reservoir.

Abstract: Memory devices include control logic configured to set a first start program voltage and a first stop program voltage, to load actual first data for cells to be programmed to a level greater than or equal to a first level, and to load inhibit data for cells to be programmed to a level less than a second level. After programming the cells to be programmed to the level greater than or equal to the first level, the control logic is further configured to set a second start program voltage and a second stop program voltage, to load inhibit data for the cells programmed to the level greater than or equal to the first level, and to load actual second data for the cells to be programmed to the level less than the second level, wherein the first level is one level higher than the second level.

Abstract: The present invention provides a data storage device that includes a flash memory and a controller. The flash memory has a plurality of TLC blocks, wherein each of the TLC blocks includes a plurality of pages. When the data storage device resumes operation after a power-off event, the controller stops writing data into a first TLC block which was undergoing a write operation that had not finished at the time the power-off event occurred, and the controller writes valid data of the first TLC block into a second TLC block after every interval of a first predetermined number of write commands is finished.

Abstract: Apparatuses for voltage level control in a semiconductor device are described. An example apparatus includes: a plurality of circuits coupled in parallel between first and second nodes, the first node being supplied with a first voltage; and a voltage supply circuit that supplies the second node with one of second and third voltages, the first voltage being greater than the second voltage, and the second voltage being greater than the third voltage. The plurality of circuits includes a first circuit including a transistor coupled to the second node. The first circuit activates the transistor responsive to a first control signal and further sets a voltage level of the second node higher than the second voltage after the voltage supply circuit supplies the second nodes with the second voltage.

Abstract: Integrated circuits with memory elements are provided. In particular, a group of random-access memory cells may be coupled to first and second data lines via corresponding access transistors. One of the first and second data lines can be driven to a ground voltage level to write a zero or one into a selected memory cell in the group. A first dummy data line can be formed adjacent to the first data line, whereas a second dummy data line can be formed adjacent to the second data line. During data loading operations, at least one of the dummy data lines can be pulsed to temporarily drive the voltage on the associated data line to below the ground voltage level. Operated in this way, the write operation of the memory cells can be improved.

Abstract: In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.

Abstract: A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; and a control gate positioned above the trapping layer.

Abstract: Methods and structures useful for magnetoresistive random-access memory (MRAM) are disclosed. The MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device also utilizes a three-terminal structure, thereby allowing efficient writing of the bit without a concomitant increase in read disturb.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a word line connected in common to gates of the memory cells, and a control circuit configured to execute a read operation on the memory cells by applying a first read voltage to the word line to determine for each of the memory cells whether or not the memory cell has a threshold voltage that is below the first read voltage and a second read voltage to the word line to determine for each of the memory cells whether or not the memory cell has a threshold voltage that is below the second read voltage. The control circuit determines the first read voltage by applying at least first to third voltages to the word line, and determines the second read voltage based on the first read voltage.

Abstract: Differential voltage generators receive an initial target voltage, and provide the initial target voltage to a first offset element and a second offset element. The first offset element includes first transistors, and the second offset element includes second transistors. Each of the first transistors is capable of changing the initial target voltage by a different incremental amount to change the initial target voltage to an altered target voltage. The second transistors are capable of removing a current generated by the first transistors, thereby causing an opposite current and leaving the initial target voltage unaffected on a second output. Each of the first transistors has a corresponding second transistor that produces the same current. A first output is capable of outputting the altered target voltage, and the second output is capable of outputting the initial target voltage.

Abstract: The load on an arbiter that conducts arbitration among host devices is reduced in an information processing system that includes the host devices and a storage device. A memory management device includes detecting units and a command generating unit. Each of the detecting units detects a timing to execute a predetermined process for the storage device. The command generating unit generates a command common to the predetermined processes subjected to the detection in the detecting units, and a sideband signal unique to each of the predetermined signals having the execution timings detected.

Abstract: A semiconductor memory device includes a memory cell including a memory magnetic tunnel junction (MTJ) configured to be coupled to a first sensing node and a reference cell including a first resistance element and a second resistance element configured to be coupled in parallel to a second sensing node, the first resistance element including a first number of reference MTJs and the second resistance element including a second number of reference MTJs different from the first number of reference MTJs. The memory device further includes a sensing circuit configured to be coupled to the first and second sensing nodes and to detect a difference in resistance between the memory cell and the reference cell. In some embodiments, the first number of reference MTJs includes first reference MTJs connected in series and the second number of reference MTJs includes second reference MTJs connected in series.

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage (Vth) of a memory cell can shift depending on when the read operation occurs. Countermeasures are provided for a first read situation in which a memory is read after a power on event or after a long delay since a last read. Read voltages of lower or higher programmed data states are set according to a positive or negative temperature coefficient (Tco), respectively. Read voltages for error recovery can be set similarly. In another aspect, a wait period between a dummy voltage and a read voltage is a function of temperature. In another aspect, word line voltages of unselected blocks are set according to a negative Tco. In another aspect, pass voltages are set based on a Tco for each programmed data state.

Abstract: Memory systems may include a memory storage, and an error correcting code (ECC) unit suitable for determining a number of unsatisfied check nodes of a channel output in a decoding iteration of a decoding process, updating a flipping indicator of a variable node, comparing the flipping indicator of the variable node with a flipping threshold associated with the decoding process, flipping a bit of the variable node when the flipping indicator is greater than the flipping threshold, and ending the decoding process when decoding is determined to be successful or a maximal iteration number is reached.

Abstract: Methods, systems, and devices for memory array operation are described. A series of pulses may be applied to a fatigued memory cell to improve performance of memory cell. For example, a ferroelectric memory cell may enter a fatigue state after a number of access operations are performed at an access rate. After the number of access operations have been performed at the access rate, a fatigue state of the ferroelectric memory cell may be identified and the series of pulses may be applied to the ferroelectric capacitor at a different (e.g., higher) rate. For instance, a delay between pulses of the series of pulses may be shorter than the delay between access operations of the ferroelectric memory cell.