Abstract: A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; and a control gate positioned above the trapping layer.

Abstract: Systems and method are directed to Universal Flash Storage (UFS) memory system configured to support deep power-down modes wherein the UFS memory system is not required to be responsive to commands received from a host device coupled to the UFS memory system. Correspondingly, in the deep power-down modes, a link or interface between the UFS memory system and the host device may also be powered down. The UFS memory system may enter the deep power-down modes based on a command received from the host device or a hardware reset assertion, and exit the deep power-down modes based on a hardware reset de-assertion or power cycling. While in deep power-down modes, the power consumption of the UFS memory device is substantially lower than the power consumption of the UFS memory device in conventional power modes.

Abstract: A method for determining quick-pass-write (QPW) operation in increment-step-program-pulse (ISPP) operation is provided. The QPW operation is simultaneously applying a bit line voltage during the ISPP operation. The method includes, according to bit line voltages varying in a first range and voltage difference values varying in a second range with respect to a verified voltage, estimating a shrinkage quantity of threshold voltage distribution width at each bit line voltage and each voltage difference value, so as to obtain a shrinkage-quantity topographic contour. According to the bit line voltages and the voltage difference values, a program shot number as needed to achieve the verified voltage is estimated, so as to obtain a program-shot-number topographic contour.

Abstract: Methods, systems, and apparatus, including medium-encoded computer program products, for analyzing data include: receiving data including responses, and lack thereof, for items of a cognitive test including multiple item-recall trials; processing the data using a stochastic model of a cognitive process, in which a conditional probability distribution of future states of the cognitive process depend upon a present state; and encoding a result of the processing on a non-transitory computer-readable medium for use in an assessment related to cognition; wherein the processing using the stochastic model includes representing recall or recognition of an item in the multiple item-recall trials using distinct cognitive states; and wherein the processing using the stochastic model includes adjusting separate memory storage and retrieval parameters for each of the distinct cognitive states in the modeled cognitive process to account for position of the items in each respective trial of the multiple item-recall trials.

Abstract: A data storage system performs operations including receiving a data read command corresponding to a first memory cell; determining whether the first memory cell is in a first read condition; if the first memory cell is in the first read condition: applying a first voltage level to the first memory cell, the first voltage level being a predetermined voltage level corresponding to a read operation for memory cells in the first read condition; and sensing a first level of current, or lack thereof, through the first memory cell during application of the first voltage level to the first memory cell; and if the first memory cell is not in the first read condition: applying a second voltage level to the first memory cell, the second voltage level being a voltage level corresponding to a read operation for memory cells in a read condition other than the first read condition.

Abstract: A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage.

Abstract: One example of a device includes a sensor, a memristor code comparator, and a controller. The sensor is to provide a sensor signal. The memristor code comparator is to compare the sensor signal to a reference signal. The controller is to determine a status of the sensor signal based on the comparison.

Abstract: According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.

Abstract: There are provided a variable resistance memory device and an operating method thereof. In a method for operating a variable resistance memory device, the method includes programming multi-bit data in a multi-bit variable resistance memory cell of the variable resistance memory device, wherein the programming includes: generating sequentially increased program voltage pulses, based on the multi-bit data; and applying the program voltage pulses to the multi-bit variable resistance memory cell, wherein a current-voltage curve of the multi-bit variable resistance memory cell exhibits a self-compliance characteristic, wherein the program voltage pulses are included in a voltage section having the self-compliance characteristic.

Abstract: Method of operating a memory include increasing respective threshold voltages of a first subset of memory cells of a plurality of memory cells to threshold voltage levels higher than a particular voltage level in response to applying a first plurality of programming pulses, and subsequently increasing respective threshold voltages of a second subset of memory cells of the plurality of memory cells to threshold voltage levels lower than the particular voltage level in response to applying a second plurality of programming pulses, wherein the first plurality of programming pulses have respective voltage levels within a first range of voltage levels, the second plurality of programming pulses have respective voltage levels within a second range of voltage levels, and a lowest voltage level of the first range of voltage levels is lower than or equal to a highest voltage level of the second range of voltage levels.

Abstract: According to one embodiment, in a semiconductor device, the first pull-up circuit is connected to a third node and to a fourth node. The third node is a node between a drain of the first transistor with a first conductivity type and a source of the second transistor with the first conductivity type. The fourth node is a node between a drain of the third transistor with the first conductivity type, and a source of the fourth transistor with the first conductivity type and a source of the fifth transistor with the first conductivity type. The first pull-down circuit is connected to a fifth node and to a sixth node. The fifth node is a node between a drain of the first transistor with a second conductivity type and a source of the second transistor with the second conductivity type.

Abstract: Program disturb is suppressed during a program recovery phase of a program operation in a memory device. The duration of the recovery phase can be increased when the risk of program disturb is greater due to factors such as temperature, the position of the selected word line, the number of program-erase cycles and the program pulse magnitude. In other approaches, the risk of program disturb is reduced by providing an early ramp down of the voltages of the drain-side word line relative to a ramp down of the voltages of the source-side word lines, providing an early ramp down of the bit line voltage of the inhibited NAND strings relative to the ramp down of the select gate voltage or setting a lower recovery voltage for the source-side word lines relative to the recovery voltage of the drain-side word lines.

Abstract: A semiconductor memory device according to an embodiment includes a plurality of strings each including a select transistor and a memory cell that can be set to any one of a plurality of different threshold voltages, a select gate line that is commonly connected to the select transistors of the plurality of strings, a plurality of bit lines that are individually connected to the plurality of strings, a word line that is commonly connected to the memory cells of the plurality of strings, and a control unit configured to execute a write sequence for repeatedly performing a plurality of loops each including a set of a program operation and a verify operation, and a voltage applied to the select gate line in the program operation of a last loop is lower than a voltage applied to the select gate line in the program operation of a first loop.

Abstract: A programming operation for high density memory, like 3D NAND flash memory, modifies the waveforms applied during program operations to mitigate unwanted disturbance of memory cells not selected for programming during the operation. Generally, the method provides for applying a bias arrangement during an interval of time between program verify pass voltages and program pass voltages in a program sequence that can include a soft ramp down, and pre-turn-on voltages designed to reduce variations in the potential distribution on floating channels of unselected NAND strings during a program operation.

Abstract: A semiconductor memory apparatus includes a word line control circuit configured to enable and disable a word line, wherein the word line control circuit comprises a switch which couples and decouples the word line to and from at least one other word line.

Abstract: A colour measurement device includes a measurement array (MA) which includes: a plurality of illumination arrays (20, 30, 40) for exposing a measurement spot (MS) on a measurement object (MO) to illumination light in an actual illumination direction (2, 3, 4) in each case, and a pick-up array (50) for detecting the measurement light reflected by the measurement spot (MS) in an actual observation direction (5) and for converting it into preferably spectral reflection factors; and a controller for the illumination arrays and the pick-up array and for processing the electrical signals produced by the pick-up array. The controller is embodied to process the measured reflection factors on the basis of a correction model, such that distortions in the measurement values as compared to nominal illumination and/or observation directions, caused by angular errors in the illumination arrays and/or the pick-up array, are corrected.

Abstract: Apparatuses, systems, and methods are disclosed for skip inconsistency correction. A skip circuit is configured to skip memory units for read operations and write operations of a memory array, based on a record of memory units identified as faulty. A skip inconsistency detection circuit is configured to detect a skip inconsistency in read data from a memory array. A correction circuit is configured to correct a skip inconsistency and output corrected read data.

Abstract: Memory systems can include shifting an ODT information signal prior to passing it through a cloned DLL delay line. The shifted ODT information passes through a cloned DLL delay line to move it into a DLL domain. Meanwhile, a clock gate can use a command indication to select whether to provide a clock signal to a DLL delay line. The clock gate can block the clock signal in the absence of a read or write operation and can pass the clock signal during read or write operations. When the DLL delay line receives the clock signal, it delays the clock signal to be in the DLL domain. By locating the ODT shifter before the cloned DLL delay line, as opposed to after it, the ODT shifter doesn't need a signal passed through the DLL delay line. Preventing the clock signal from passing through the DLL delay line reduces power consumption.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a word line connected in common to gates of the memory cells, and a control circuit configured to execute a read operation on the memory cells by applying a first read voltage to the word line to determine for each of the memory cells whether or not the memory cell has a threshold voltage that is below the first read voltage and a second read voltage to the word line to determine for each of the memory cells whether or not the memory cell has a threshold voltage that is below the second read voltage. The control circuit determines the first read voltage by applying at least first to third voltages to the word line, and determines the second read voltage based on the first read voltage.

Abstract: A data storage apparatus and a method for preventing data error using the same are provided. The data storage apparatus includes a memory and a memory controller. The memory includes a plurality of blocks. The memory controller is coupled to the memory and configured to perform the following operations: recording a read count of a target block of the memory; performing an error bit check on a free storage space of the target block when the read count of the target block meets a condition; and programming a dummy data to the free storage space of the target block in response to the determination that the check result is negative.