Abstract: A lead frame used for the production of a semiconductor package, wherein each of terminals of the lead frame to be wire-bonded to electrodes provided on the top surface of the semiconductor device has one or two groove(s) for limiting a plating area of noble metal. Since grooves are provided in each terminal, the accuracy of the plating area can be easily checked visually. Further, the grooves absorb stress applied to the terminal when the molded semiconductor packages are individually separated from each other by punching or dicing, and the situation where molding compound comes off of the terminal is prevented. In addition, since the grooves absorb vibrational stress applied to the terminal after mounting a semiconductor on the printed circuit board, the reliability of assembly is improved.

Abstract: A multi-die semiconductor package having an electrical interconnect frame. A top integrated circuit die is attached to the top side of an upper contact level of the frame and a bottom integrated circuit die is attached to the bottom side of the upper contact level of the frame. The die bond pads of the top die are electrically coupled (e.g. wired bonded) to pads of a lower contact level of the interconnect frame. The die bond pads of the bottom integrated circuit die are electrically coupled (e.g. wired bonded) to bond pads of the upper contact level of the frame. The bond pads of the lower contact level serve as external bond pads for the package. The frame may include inset structures, each having an upper portion located in the upper contact level and a lower portion located in the lower contact level.

Abstract: In accordance with the present invention, there is provided a semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and including at least two slots formed therein and extending along respective ones of a pair of the peripheral edge segments thereof. The semiconductor package further comprises a plurality of first leads which are segregated into at least two sets disposed within respective ones of the slots included in the die paddle. In addition to the first leads, the semiconductor package includes a plurality of second leads which are also segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the die paddle in spaced relation thereto. Electrically connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of each of the first and second leads.

Abstract: A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interlevel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interlevel dielectric layer, a top surface of the bottom electrode co-planer with a top surface of the interlevel dielectric layer; a conductive diffusion barrier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. The conductive diffusion barrier may be recessed into the copper bottom electrode or an additional recessed conductive diffusion barrier provided. Compatible resistor and alignment mark structures are also disclosed.

Abstract: A substrate provided with an alignment mark in a substantially transmissive process layer overlying the substrate, said mark comprising at least one relatively high reflectance area(s) for reflecting radiation of an alignment beam of radiation, and relatively low reflectance areas for reflecting less radiation of the alignment beam, wherein the high reflectance area(s) is (are) segmented in first and second directions both directions being substantially perpendicular with respect to each other so that the high reflectance areas comprise predominantly rectangular segments.

Abstract: A coin-shaped IC tag which can be endowed with a predetermined weight is described. The coin-shaped IC tag ensures a normal operation and affords a satisfactory feeling of weightiness as a value medium. Methods of manufacturing the coin-shaped IC tag are also described. The coin-shaped IC tag comprises an IC tag core. The IC tag core comprises an IC packaging base member including a base and an electronic circuit for communicating data and for recording data, the electronic circuit mounted on the base. The IC tag core also comprises a high specific gravity resin layer joined to the IC packaging base member.

Abstract: A semiconductor device includes a semiconductor chip with a functional surface, a substrate opposing the functional surface of the semiconductor chip at a space formed between the substrate and the functional surface, a power supplying device electrically connected to a part of the functional surface of the semiconductor chip and separated by a slight gap from the substrate, a fixing member that fixes the semiconductor chip to the substrate, and a sealing member that seals the space formed between the substrate and the functional surface of the semiconductor chip other than a space formed between the substrate and the functional surface of the semiconductor chip that are fixed to each other through the fixing member and other than the gap formed between the power supplying device and the substrate. The sealing member has greater elasticity than the fixing member.

Abstract: A high aspect ratio contact structure formed over a junction region in a silicon substrate comprises a titanium interspersed with titanium silicide layer that is deposited in the contact opening and directly contacts an upper surface of the substrate. Silicon-doping of CVD titanium, from the addition of SiH4 during deposition, reduces consumption of substrate silicon during the subsequent silicidation reaction in which the titanium reacts with silicon to form a titanium silicide layer that provides low resistance electrical contacts between the junction region and the silicon substrate. The contact structure further comprises a titanium nitride contact fill that is deposited in the contact opening and fills substantially the entire contact opening.

Abstract: An embodiment of the present invention described and shown in the specification and drawings is a process and a package for facilitating cooling and grounding of a semiconductor die using carbon nanotubes in a thermal interface layer between the die and a thermal management aid. The embodiments that are disclosed have the carbon nanotubes positioned and sized to utilize their high thermal and electrical conductance to facilitate the flow of heat and current to the thermal management aid. One embodiment disclosed has the carbon nanotubes mixed with a paste matrix before being applied. Another disclosed embodiment has the carbon nanotubes grown on the surface of the semiconductor die.

Abstract: A method of manufacturing a semiconductor component and the component thereof includes forming a dielectric layer (620) over a portion of a passivation ledge (640) in an emitter layer (280) and overlapping a base contact (660) onto the dielectric layer (620).

Abstract: A semiconductor device including a gate oxide of multiple thicknesses for multiple transistors where the gate oxide thicknesses are altered through the growth process of implanted oxygen ions into selected regions of a substrate. The implanted oxygen ions accelerate the growth of the oxide which also allow superior quality and reliability of the oxide layer, where the quality is especially important, compared to inter-metal dielectric layers. A technique has been used to vary the thickness of an oxide layer grown on a silicon wafer during oxidation growth process by implanting nitrogen into selected regions of the substrate, which the nitrogen ions retard the growth of the silicon oxide resulting in a diminished oxide quality. Therefore it is desirable to fabricate a semiconductor device with multiple thicknesses of gate oxide by the implanted oxygen ion technique.

Abstract: An optical semiconductor device with a multiple quantum well structure, is set out in which well layers and barrier layers, comprising various types of semiconductor layers, are alternately layered. The device well layers comprise a first composition based on a nitride semiconductor material with a first electron energy. The barrier layers comprise a second composition of a nitride semiconductor material with electron energy which is higher in comparison to the first electron energy. The well and barrier layers are in the direction of growth, by a radiation-active quatum well layer which with the essentially non-radiating well layers (6a) and the barrier layers (6b), arranged in front, form a supperlattice.

Abstract: An IC chip has externally and selectively cuttable members F1-F3, which can be cut, or cut open, at more than one cuttable points C1 and C2. So long as at least one of the multiple cuttable points C1 and C2 remains cut open, the cuttable member works as a cut member. Thus, a cut member has an exceedingly small probability that it is short-circuited by particles in an ACF or by dust.

Abstract: A silicon device which includes a silicon substrate and a bond pad array on the silicon substrate which is configured to be conductively connected to bond wire. The bond pad array consists of a plurality of bond pads which are vertically staggered on the silicon substrate. The vertical staggering allows the bond pads to be packed closer together on the silicon substrate, thereby reducing the horizontal space which is consumed by the bond pads on the silicon substrate, and thereby resulting in a reduction in die size. Preferably, the bond pads are also horizontally staggered on the silicon substrate, thereby allowing the bond pads to be spaced even closer together.

Abstract: A semiconductor material which has a high carbon dopant concentration includes gallium, indium, arsenic and nitrogen. The disclosed semiconductor materials have a low sheet resistivity because of the high carbon dopant concentrations obtained. The material can be the base layer of gallium arsenide-based heterojunction bipolar transistors and can be lattice-matched to gallium arsenide emitter and/or collector layers by controlling concentrations of indium and nitrogen in the base layer. The base layer can have a graded band gap that is formed by changing the flow rates during deposition of III and V additive elements employed to reduce band gap relative to different III-V elements that represent the bulk of the layer. The flow rates of the III and V additive elements maintain an essentially constant doping-mobility product value during deposition and can be regulated to obtain pre-selected base-emitter voltages at junctions within a resulting transistor.

Abstract: An encapsulant for use with opto-electronic devices and optical components incorporates a filler made from a glass that has been processed into particle form and heated to a predetermined temperature for a predetermined time, along with an epoxy having an index of refraction matched to that of the glass and heated to a predetermined temperature for a predetermined time, to prevent settling of the filler particles after mixing the filler particles with the epoxy, and thereby obtaining uniform dispersion of the particles within the epoxy. The encapsulant provides for high light transmittance, and its coefficient of thermal expansion can be varied by varying the amount of filler without substantially altering the optical properties of the encapsulant. The coefficient of thermal expansion variation within the encapsulant preferably is less than 30%, due to uniform dispersion of the filler particles within the epoxy.

Abstract: A semiconductor package has a substrate comprising a resin layer of an approximate planar plate, a cavity passing through the resin layer vertically at a center area thereof, a plurality of electrically conductive patterns formed at a bottom surface of the resin layer, and a conductive plan. An adhesive layer of a predetermined thickness is formed at an upper part of an inside of the cavity. A semiconductor die is positioned inside the cavity of the substrate and has a plurality of bond pads formed at a bottom surface thereof, a bottom surface of the adhesive layer being bonded to a top surface thereof. A plurality of conductive wires for electrically connecting the bond pads of the semiconductor die to the electrically conductive patterns are formed at a bottom surface of the substrate. An encapsulant is used for covering the semiconductor die formed at the lower part of the adhesive layer, the conductive wires and the cavity.

Abstract: There are provided the steps of forming a plurality of opening portions by punching predetermined portions of a metal plate, forming crushed portions by pushing crushed margin portions, which are defined in vicinity of both side edge portions of the opening portions of the metal plate, to reduce a thickness, defining a width W3 between a side surface portion and a center portion to assure an interval between lead portions and also defining a width of a top end portion and a width of a base portion by punching center portions of the crushed portions except predetermined both-side portions and portions in vicinity of peripheral portions in which the crushed portions of the opening portions of the metal plate are not present, and defining the top end portions by punching a predetermined portion of the top end portion.

Abstract: A mounting substrate includes a substrate body having at least first and second adjacent chip mounting regions on a surface thereof, and a dicing line between the first and second mounting regions; a first plurality of inner electrodes aligned along a first side of the first chip mounting region; a second plurality of inner electrodes aligned along a second side of the second chip mounting region, wherein the first side of the first chip mounting region confronts the second side of the second chip mounting region; and an interconnect wiring pattern located between the first and second chip mounting regions, and commonly connected to the first plurality of inner electrodes and the second plurality of inner electrodes, wherein the interconnect wiring pattern includes a plurality of connecting wiring portions and at least some of the wiring pattern extends obliquely across the dicing line.

Abstract: A high-frequency semiconductor device is provided with a ceramic substrate, an element group including semiconductor elements and passive components mounted onto a bottom portion of the ceramic substrate, and a composite resin material layer formed on the bottom portion of the ceramic substrate so as to bury the element group. The composite resin material layer is formed by a composite resin material including an epoxy resin and an inorganic filler material, and has a flat bottom surface on which electrodes for connecting to the outside are formed. As packaging of a structure in which the receiving system and the transmitting system are formed in a single unit, such as an RF module, the high-frequency semiconductor device achieves a small size, a high mounting density, and excellent heat release properties.