Abstract: A cellularly constructed semiconductor component has a connection electrode, which contact-connects some of the cells, and a connection line, which contact-connects the connection electrode. In which case, in a region at a distance from a connection contact between the connection line and the connection electrode, at least some of the cells are not connected to the connection electrode.

Abstract: A matrix array device, for example, an active matrix display device, image sensor, or the like, comprises a matrix circuit (12, 14, 16, 18) carried on a flexible substrate (20) which circuit includes an array of semiconductor devices (12), such as TFTs, occupying discrete areas. Selected regions of the substrate (20) away from the semiconductor devices (12) are formed as areas of weakness to encourage flexing of the substrate to occur preferentially at those regions upon bending of the device and so reduce the risk of damage to the semiconductor devices. The regions, for example, may comprise lines of weakness (50, 52) extending between the semiconductor devices and may be formed by localized thinning of the substrate or by treating the substrate material to modify its stiffness at predetermined areas.

Abstract: A semiconductor package includes a semiconductor chip having a major surface and first pads formed on the major surface. The semiconductor package also includes a package substrate having (a) opposite first and second major surfaces, (b) a side surface extending between the first and second major surfaces, (c) a pad forming region adjacent to and along the side surface, (d) second pads formed on the pad forming region, (e) external electrodes formed on the first major surface of the package substrate, wherein the second major surface of the package substrate is fixed to the major surface of the semiconductor chip, and wherein the external electrodes are electrically connected to the second pads. The semiconductor package further includes bonding wires electrically connecting the first pads to the second pads and a sealing material covering the bonding wires and first and second pads.

Abstract: A low resistance buried back contact for SOI devices. A trench is etched in an insulating layer at minimum lithographic dimension, and sidewalls are deposited in the trench to decrease its width to sublithographic dimension. Conducting material is deposited in the trench, which serves as a low-resistance contact to the back side of the device. In another embodiment, the trench-fill material is separated from the device by an insulating layer, and serves as a back gate structure.

Abstract: The invention relates to an electronic chip component and a method for fabricating the chip component with a semiconductor chip having an integrated circuit therein. Contact surfaces are on the active surface of the semiconductor chip. The contact surfaces of the integrated circuit have a contact layer consisting of pressure contact material, which protrudes beyond the level of the top non-conductive layer. The active surface of the semiconductor chip includes a meltable glue layer that is adapted to the height of the contact layer.

Abstract: Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.

Abstract: A method and apparatus for assembling and packaging semiconductor dice. The semiconductor dice or assemblies of stacked and electrically interconnected semiconductor dice are placed at mutually spaced locations with respect to a common plane and encapsulated in a dielectric material so that end portions of discrete conductive elements extending outwardly from each semiconductor die adjacent the common plane are exposed through an outer surface of the dielectric material. Redistribution lines are formed to extend from the exposed end portions of the discrete conductive elements to predetermined locations over the outer surface of the encapsulant which correspond with another interconnect outline, such as terminal pads of a printed circuit board, and conductive bumps formed at the predetermined locations.

Abstract: A highly reliable semiconductor device less susceptible to external noise is provided. The semiconductor device has a signal output chip and a substrate. The signal output chip has one or more semiconductors and outputs a predetermined signal. The substrate has a circuit formed thereon and is electrically connected to the signal output chip. A potential of the substrate is fixed to a certain level.

Abstract: The invention encompasses microelectronic package lids, heat spreaders, and semiconductor packages comprising microelectronic lids or heat spreaders. In particular aspects of the present invention, a microelectronic lid comprises a material having a rectangular peripheral shape that defines 4 peripheral sides. Further, the lid has projecting peripheral rails along less than all of the peripheral edge. For instance, the lid can have projecting peripheral rails along only 2 of the sides. Alternatively, such microelectronic lid can be described as comprising a generally rectangular shape defining four peripheral edges, with two of the edges having a greater thickness than the other two edges.

Abstract: Flash memory cells are provided that include a first source/drain region and a second source/drain region separated by a channel region. A first gate opposes. A first gate insulator separates the first gate from the channel. The first gate insulator includes a graded composition gate insulator. A second gate is separated from the first gate insulator by a second gate insulator. The above memory cells produce gate insulators with less charging at the interface between composite insulator layers and provide gate insulators with low surface state densities. The memory cells substantially reduce large barrier heights or energy problems by using dielectrics having suitably, adjustably lower barrier heights in contact with the polysilicon floating gate. Such adjustable barrier heights of controlled thicknesses can be formed using a silicon suboxide and a silicon oxycarbide dielectrics prepared according to the process as described herein.

Abstract: The present invention provides flip-chip packaging for optically interactive devices such as image sensors and methods of assembly. In a first embodiment of the invention, conductive traces are formed directly on the second surface of a transparent substrate and an image sensor chip is bonded to the conductive traces. Discrete conductive elements are attached to the conductive traces and extend below a back surface of the image sensor chip. In a second embodiment, a secondary substrate having conductive traces formed thereon is secured to the transparent substrate. In a third embodiment, a backing cap having a full array of attachment pads is attached to the transparent substrate of the first embodiment or the secondary substrate of the second embodiment. In a fourth embodiment, the secondary substrate is a flex circuit having a mounting portion secured to the second surface of the transparent substrate and a backing portion bent over adjacent to the back surface of the image sensor chip.

Abstract: A semiconductor wafer comprises a semiconductor substrate, a surface alignment mark visible on the semiconductor surface and a plurality of nanostructures on the surface of the surface alignment mark having an average pitch adapted to reduce reflectivity of the surface alignment mark in a predetermined light bandwidth.

Abstract: A first level metal interconnection line in a layer below a third level metal interconnection line serving as a main word line MWL is used as a shunting interconnection line and electrically connected to a first level polysilicon interconnection line constituting a sub word line SWL at prescribed intervals. By applying a hierarchical word line structure and a word line shunting structure both, a word line is driven into a selected state at high speed without increasing an array occupancy area and manufacturing steps.

Abstract: The present invention relates to a semiconductor device arranged at a surface of a semiconductor substrate having an initial doping having an electrical connection comprising at least one plug made of a material with a high conductivity, especially a material other than the substrate, especially a metal plug, between said initially doped substrate and said surface of the substrate. The device has at least one ground connection arranged to be connected to a ground pin on a package. The ground connection is arranged to be connected to said ground pin using said electrical connection, where the initially doped substrate is arranged to be connected to said ground pin via a reverse side of the substrate, opposite said surface, and thereby being arranged to establish a connection between said ground connection and said ground pin.

Abstract: A small-sized semiconductor light-emitting device of high emission directivity and high output is provided. A portion of a light extraction section of a semiconductor light-emitting device including a pn-junction portion is covered with a light-shielding substance of low conductivity. The electrical resistance of the light-shielding substance is 106 ?m or higher, and the substance contains powder of at least one species selected from metals and pigments. The powder of metal contains at least one species selected from among Al, Cu, Ag, Au, Pt, Ti, Ni, Sn, Pb, Mg, Zn, Fe, Co, and Cr. The powder is a plate-like powder having a thickness falling within a range of 0.001-10 ?m and a length falling within a range of 0.01-100 ?m.

Abstract: A spiral inductor comprising: a substrate; a protruding portion which is formed on the top face of the substrate and the top of which serves as a dummy element for controlling a chemical mechanical polishing process; and a conductive layer which is formed on the substrate so as to have a spiral shape and which serves as an induction element, wherein the protruding portion is formed in a region other than a region directly below the conductive layer.

Abstract: In a wiring structure in which a wiring portion and a plug portion each made of a Cu material are formed integrally through a damascene process, the difference between deviation stress applied to the wiring portion in a longitudinal direction and deviation stress applied to the plug portion in a direction perpendicular to the central axis of the plug portion is controlled to be 220 MPa or less.

Abstract: In the forms of a flip-chip package in which the contact elements of the chip are ultrasonically welded to the contact elements of the substrate, either the chip or the substrate or both are provided, prior to juxtaposition, with a bonding material which can be ultrasonically activated. During the ultrasonic welding process in which the contact elements of the chip and substrate are bonded together, the bonding material provides an additional attachment between the chip and substrate and eliminates the need for underfilling.

Abstract: A substrate and a fabrication method thereof are proposed, with at least a check point being formed on the substrate. Prior to wire bonding and/or molding processes, cleanness of the substrate (cleaned by plasma) is determined according to color variation of the check point, so as to allow only cleaned and contamination-free substrates to be subsequently formed with bonding wires and encapsulants thereon. Thereby, qualities of wire-bonded electrical connection and encapsulant adhesion for the substrate can be assured, which helps prevent the occurrence of delamination between the encapsulant and the substrate. Moreover, the check point formed on the substrate is made during general substrate fabrication by using current equipment and technique, and in a manner as not to interfere with trace routability on the substrate; thereby, costs and complexity of substrate fabrication would not undesirably increased.

Abstract: Novel semiconductor devices containing a discontinuous cap layer and possessing a relatively low dielectric constant are provide herein. The novel semiconductor devices includes at least a substrate, a first dielectric layer applied on at least a portion of the substrate, a first set of openings formed through the dielectric layer to expose the surface of the substrate so that a conductive material deposited within and filling the openings provides a first set of electrical contact conductive elements and a discontinuous layer of cap material covering at least the top of the conductive elements to provide a first set of discontinuous cap elements. Methods for forming the semiconductor devices are also provided.