Abstract: The traditional nitride-only charge storage layer of a SONOS device is replaced by a multifilm charge storage layer comprising more than one dielectric material. Examples of such a multifilm charge storage layer are alternating layers of silicon nitride and silicon dioxide, or alternating layers of silicon nitride and aluminum oxide. The use of more than one material introduces additional barriers to migration of charge carriers within the charge storage layer, and improves both endurance and retention of a SONOS-type memory cell comprising such a charge storage layer.

Abstract: A semiconductor device allows a second seal portion 8 made of a conductive resin to function as an electromagnetic wave shield for a photodetector 3 and a control IC chip 5 sealed with a first seal portion 7 made of a light-transmitting resin, when a third lead 1c for grounding of a lead frame 1 is connected to a ground terminal on a board. Conductive portions 21, 22 of the second seal portion 8 fill through holes 16, 17 provided for projecting portions 10, 11 of the lead frame 1 so as to be in close contact with peripheral surfaces 16A, 17A of the through holes 16, 17. The through holes 16, 17 have peripheral surfaces 16A, 17A of a rectangular-columnar shape. The semiconductor device is capable of obtaining a sufficient electromagnetic shielding effect, while it is small and low-cost, having a high degree of mounting freedom on a board.

Abstract: A rectification chip terminal structure for soldering a rectification chip encased in a glass passivated pallet (GPP) on a terminal filled with a packaging material to form a secured mounting for the rectification chip is to be inserted in a coupling bore of a circuit board. The structure includes a conductive element which has a buffer portion and a base seat to prevent the GPP from fracturing when the packaging material is heated and expanded or prevent the conductive element from bending and deforming under external forces, and has a stress buffer zone to prevent the chip from being damaged and moisture from entering. It can prevent the GPP from fracturing when the packaging material is heated and expanded and be installed easily in the coupling bore of the circuit board and hold the packaging material securely without breaking away.

Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.

Abstract: There is here disclosed a semiconductor device manufacturing method comprising a step of forming an island region including a monocrystalline Si1-x-yGexCy layer (1>x>0, 1>y?0) and a peripheral region including an amorphous or polycrystalline Si1-x-yGexCy layer which surrounds the island region on a monocrystalline Si layer on an insulating film, a step of subjecting the respective Si1-x-yGexCy layers to heat treatment, and after the heat treatment and the removal of a surface oxide film, a step of forming a monocrystalline Si1-z-wGezCw layer (1>z?0, 1>w?0) which becomes an element formation region on the island region.

Abstract: A semiconductor device includes a silicon layer on an insulating layer. The silicon layer has a first area and a second area. An FD-MOSFET is formed in the first area and a PD-MOSFET is formed in the second area. The semiconductor device satisfies the following formulas: the thickness of the silicon layer is 28 nm to 42 nm, the impurity concentration Df cm?3 of the first area is Df?9.29*1015*(62.46?ts) and Df?2.64*1015*(128.35?ts), and the impurity concentration Dp of the second area is Dp?9.29*1015*(62.46?ts) and Dp?2.64*1015*(129.78?ts).

Abstract: A semiconductor device having at least two layers formed on a semiconductor substrate includes a first dielectric layer formed on the semiconductor substrate; a first interconnection layer which is formed on the first dielectric layer and has a first interconnection pattern and a dummy pattern formed around the first interconnection pattern; a second dielectric layer formed on the first interconnection layer; and a second interconnection layer which is formed on the second dielectric layer and has a second interconnection pattern. The dummy pattern is placed in the vicinity of only an area where the first and second interconnection patterns are superposed on each other.

Abstract: Off-chip driver (OCD) NMOS transistors with ESD protection are formed by interposing an P-ESD implant between the N+ drain regions of OCD NMOS transistors and the N-well such that the P-ESD surrounds a section of the N-well. The P-ESD implant is dosed less than the N+ source/drain implants but higher than the N-well dose. In another embodiment, N-well doping is used along with P-ESD doping, where the P-ESD doping is chosen such that it counterdopes the N-well underneath the N+ drains. The N-well, however, still maintains electrical connection to the N+ drains. This procedure creates a larger surface under the area where the junction breakdown occurs and an increased radius of curvature of the junction. The P-ESD implant is covered by N-type on three sides creating better parasitic bipolar transistor characteristics.

Abstract: An illuminator (1) comprises a substrate (2) supporting light source dies (4) driven via wire bonds (5). The substrate (2) comprises a silicon strip (20) in direct contact with a brass heat sink (3), thus providing for excellent heat transfer away from the die (4). Pads (10, 11, 12) of Ni, Ti, and Ag sub-layers support the die (4) and the wire bonds (5). These both provide electrical connections for the die (4) and also light reflection upwardly because the Ag sub-layers of the pads (10, 11, 12) are evaporated over a thermally grown oxide layer (21) on the Si (20). The oxide has a very high dielectric strength, thus maintaining excellent electrical insulating properties over a large voltage range.

Abstract: In accordance with the present invention, there is provided a semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and including at least two slots formed therein and extending along respective ones of a pair of the peripheral edge segments thereof. The semiconductor package further comprises a plurality of first leads which are segregated into at least two sets disposed within respective ones of the slots included in the die paddle. In addition to the first leads, the semiconductor package includes a plurality of second leads which are also segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the die paddle in spaced relation thereto. Electrically connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of each of the first and second leads.

Abstract: The invention reduces the resistance of a feed line in a display device (electro-optical device), and reduces the loss in the current supply to a light-emitting element, etc. In an electro-optical device including an electro-optical element and a driver circuit to drive the electro-optical element, a wiring board used for the electro-optical device includes a feed line film to supply the driver circuit with current to put the electro-optical element into operation; a signal line film to supply the driver circuit with a level signal to determine intensity of the current to be supplied to the electro-optical element; and an operation line film to supply the driver circuit with an operation instruction signal to instruct whether to put the electro-optical element into operation, and the feed line film constitutes an upper layer among the feed line film, the signal line film, and the operation line film.

Abstract: A dual-side thermal interface and cooling design of an integrated power module is disclosed which effectively reduces the equivalent thermal impedance on the power module by 20%. This in turn reduces the temperature rise of the junction temperature of the power devices inside the power module by 20% with an equivalent load current. As a consequence the weight and volume associated with the conventional cooling mechanism not employing a dual thermal interface is reduced, thus increasing the ambient operating temperature limit of a power converter in the module.

Abstract: The present invention provides for low cost discrete inductor devices in an all organic platform. The inductor devices can utilize virtually any organic material that provides the desired properties, such as liquid crystalline polymer (LCP) or polyphenyl ether (PPE), in a multilayer structure, wherein the organic materials have low moisture uptake and good temperature stability. Each layer may be metalized and selectively interconnected by vias formed in respective layers so as to form winding or coiled inductors. The inductor devices may advantageously include external shielding formed by metalizing the side walls and top surface of the inductor devices on in-built shielding achieved by the utilization of the hybrid co-planar waveguide topologies. The inductor devices can be configured for either ball grid array (BGA)/chip scale package (CSP) or surface mount device (SMD) mounting to circuit boards.

Abstract: A leadframe includes: a frame rail; a die pad, disposed inside the frame rail, for mounting a semiconductor chip thereon; and a plurality of internal inner leads, which are disposed to surround the die pad and each of which has a convex portion on the bottom thereof. The frame rail and the internal inner leads are retained by a lead retaining member on their upper and/or lower surface(s).

Abstract: A semiconductor device has a ferroelectric capacitor. The semiconductor device includes an interlayer insulating layer, a ferroelectric capacitor and an insulating side wall film. The interlayer insulating layer is formed on a substrate including an integrated circuit and has a contact hole exposing a part of the integrated circuit. The ferroelectric capacitor is formed by depositing a first electrode layer, a ferroelectric layer and a second electrode layer on the interlayer insulating layer in this order. The insulating side wall film covers a peripheral edge section of the ferroelectric capacitor and is spaced from a peripheral edge section of the contact hole. A wiring layer electrically connects the second electrode layer to the integrated circuit through the contact hole.

Abstract: A semiconductor device comprises a semiconductor IC chip provided with bond pads on its first surface, a wiring substrate provided with a through hole extending between the opposite surfaces thereof, conductive members electrically connecting the bond pads of the semiconductor IC chip to the conductive lines formed on the wiring substrate respectively, and a sealing resin coating coating the first surface of the semiconductor IC chip and the conductive members, and bonding the side surface of the semiconductor IC chip to the side surface of the through hole of the wiring substrate.

Abstract: A semiconductor device includes a substrate, a plurality of bump electrodes disposed on the substrate, and a support area for supporting the substrate in case of carrying the substrate. The support area is disposed on a surface of the substrate, on which the bump electrode is disposed, and is disposed at a predetermined position, which is dotted on the surface of the substrate. In this device, the support area is sufficiently small, and the number of the bump electrodes can increase. Moreover, degree of freedom in a configuration of the support area increases.

Abstract: The memory cell according to the invention has a vertical selection transistor, via whose channel region the inner electrode of the trench capacitor can be connected to a bit line. The large extent of the channel region in the bit line direction means that the trench capacitor can be rapidly charged and read. The channel region is led to the bit line through an associated word line, which completely or partially encloses the channel region. A conductive channel can be formed within the channel region depending on the potential of the word line.

Abstract: A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier layer, and the via structure include a seed layer, a diffusion barrier layer and a metal plug. The via seed layer is controlled to a thickness that discourages the reaction between the via seed layer and the bulk conductor layer. The reaction may result in the formation of harmful voids at the bottom of the vias and is caused by having the via seed metal coming in contact with the bulk conductor through openings in the barrier layer.

Abstract: A memory cell array has memory cells arranged in a matrix form. The memory cell includes a floating gate and a control gate. Word lines are each coupled to the control gates of the memory cells which are arranged on a corresponding one of the rows in the memory cell array. Bit lines are each coupled to drains of the memory cells which are arranged on a corresponding one of the columns in the memory cell array. An external voltage is supplied from the exterior to an external voltage input terminal. A first voltage generating circuit lowers the external voltage to generate a voltage which is to be supplied to the word line coupled to the control gates. A second voltage generating circuit lowers the external voltage to generate a voltage which is to be supplied to the bit line coupled to the drains.