Abstract: A slot design for a metal interconnect line comprising a metal interconnect including at least two metal sub-interconnect lines that intersect to form an intersection area. At least one of the metal sub-interconnect lines having elongated slots formed therein with the elongated slots each having an axis extending through the intersection area. The intersection area having an effective cross-sectional area that is at least equal to the effective cross-sectional area of at least one of the metal sub-interconnect lines having elongated slots formed therein.

Abstract: A power module incorporates a switching semiconductor element and a smoothing capacitor and includes a metallic base plate dissipating heat produced by the switching semiconductor element and the smoothing capacitor. The metallic base plate is thermally separated into a first region adjacent to the switching semiconductor element and a second region adjacent to the smoothing capacitor.

Abstract: A circuit device and a method for fabrication the same is provided. An insulation resin sheet in which the first conductive layer 3 and the second conductive layer 4 are adhered to each other by insulation resin 2 is used. The first conductive path layer 5 is formed by the first conductive layer 3, the second conductive path layer 6 is formed by the second conductive layer 4, and both of the conductive path layers are connected by multi-layer connecting means 12. Since a semiconductor element 7 is adhered to and fixed on overcoating resin 8 that covers the first conductive path layer 5, a multi-layer connection structure can be achieved by the first conductive path layer 5 and the second conductive path layer 6. Further, the second conductive layer 4 that is made thick can prevent warping from occurring due to a difference in a thermal expansion coefficient.

Abstract: A capacitor and a method of manufacturing the same are disclosed. The BST dielectric film is disposed between the lower electrode by coating a sidewall of the upper electrode and then forming the lower electrode in a second contact hole defined by the upper electrode and BST film. As such, degradation in the step coverage characteristic caused by forming a BST dielectric film having a desired composition ratio is avoided.

Abstract: A bendable light emitting diode (LED) array in accordance with the present invention includes heat spreaders, dielectric material disposed above each heat spreader, and a bendable electrical interconnection layer disposed above these heat spreaders and electrically insulated from these heat spreaders by the dielectric material. At least one via passes through the dielectric material above each heat spreader, and at least one LED die is disposed above each via. The bendable electrical interconnection layer may be a lead frame comprising metal pathways that electrically interconnect some or all LED dice in series, in parallel, in anti-parallel, or in some combination of these configurations. Each via contains a thermally conductive material in thermal contact with the corresponding heat spreader below it and in thermal contact with the corresponding LED die above it. The LED dice may be thermally and electrically coupled to submounts disposed above corresponding heat spreaders in some embodiments.

Abstract: A structure of and a method for making an isolated NMOS transistor using standard BiCMOS processing steps and techniques. No additional masks and processing steps are needed for the isolated NMOS device relative to the standard process flow. A P-type substrate with an overlaying buried N-type layer overlaid with a buried p-type layer below a P-well is shown. An N-type region surrounds and isolates the P-well from other devices on the same wafer. N+ regions are formed in the p-well for the source and drain connections and poly or other such electrical conductors are formed on the gate, drain and source structures to make the NMOS device operational. Parasitic bipolar transistors are managed by the circuit design, current paths and biasing to ensure the parasitic bipolar transistors do not turn on.

Abstract: A semiconductor package exhibiting efficient placement of semiconductor leads in a micro lead frame design is provided. An integrated circuit die is bonded to the top surfaces of leads, thereby allowing the leads to partially reside under the die. As a result, surface area on the bottom surface of the semiconductor package is recaptured. The die can be further bonded a die paddle if so desired. One or more channels can be cut into the bottom surface of the package in order to separate first and second leads. Such channels allow separate leads to be fabricated from a single lead member which is subsequently cut.

Abstract: An integrated circuit is electrically connected with a plurality of pads. A passivation film covers a part of each of the pads and exposes the other part of each of the pads. Bumps are formed on the pads, respectively. Each of the bumps is a single layer disposed on a part of each of the pads exposed from the passivation film, and on the passivation film.

Abstract: The invention relates to the field of electronic devices with a thermally conducting encapsulant for draining away some of the energy dissipated by the electronic components contained in the electronic device.

Abstract: A microelectronic package including a microelectronic die having through silicon vias extending through a back surface thereof, which allows both an active surface and the back surface of the microelectronic die to have power, ground, and/or input/output signals connected to a flexible substrate. The flexible substrate may further connected to an external substrate through at least one external contact.

Abstract: A plastic ball grid array package has a heat slug which is placed onto the substrate, which has the semiconductor device attached, prior to encapsulation. The heat transfer member is initially located by guide pins and fixed in place by the encapsulation.

Abstract: A MOS semiconductor device includes n?-type surface regions, which are extended portions of an n?-type drift layer 12 extended to the surface of the semiconductor chip. Each n?-type surface region 14 is shaped with a stripe surrounded by a p-type well region. The surface area ratio between n?-type surface regions 14 and p-type well region 13 including an n+-type region 15 is from 0.01 to 0.2. The MOS semiconductor device further includes, in the breakdown withstanding region thereof, a plurality of guard rings, the number of which is equal to or more than the number n calculated from the following equation n=(Breakdown voltage Vbr (V))/100, and the spacing between the adjacent guard rings is set at 1 ?m or less.

Abstract: A small-sized, light-weight, low-cost power semiconductor device with excellent productivity and vibration resistance is obtained. A mold resin casing (1) is made of a thermosetting resin, such as epoxy resin, and has a top surface (1T) and a bottom surface (1B). A through hole (2) is formed in a non-peripheral portion (in this example, approximately in the center) of the mold resin casing (1) to pass through between the top surface (1T) and the bottom surface (1B). Electrodes (3N, 3P, 4a, 4b) have their first ends projected from sides of the mold resin casing (1). The bottom surface (5B) of a heat spreader (5) is exposed in the bottom surface (1B) of the mold resin casing (1). The heat spreader (5) has an opening (6) formed around the through hole (2).

Abstract: An electrical connector is formed from a sheet of electrically conductive material that lies in between the two layers of nonconducting material that comprise the casing of an electrical chip. The connector is electrically connected to an electrical element embedded within the chip. An opening in the sheet is concentrically aligned with a pair of larger holes respectively bored through the nonconducting layers. The opening is also smaller than the diameter of an electrically conductive contact pin. However, the sheet is composed flexible material so that the opening adapts to the diameter of the pin when the pin is inserted therethrough. The periphery of the opening applies force to the sides of the pin when the pin is inserted, and thus holds the pin within the opening and in contact with the sheet, by friction. The pin can be withdrawn from the connector by applying sufficient axial force.

Abstract: A test structure of a DRAM array includes a substrate. A transistor is formed on the substrate and has a first region and a second region as source/drain regions thereof. A deep trench capacitor is formed adjacent to the transistor and has a first width. A shallow trench isolation is formed in a top portion of the deep trench capacitor and has a second width. The second width is substantially shorter than the first one. A third region is formed adjacent to the deep trench capacitor. A first contact is formed on the substrate and contacts with the first region. A second contact is formed on the substrate and contacts with the third region.

Abstract: A semiconductor package including a dam and a method for fabricating the same are provided. The semiconductor package comprises a package substrate, a semiconductor chip attached to the substrate, a TIM formed on the semiconductor chip, a dam that substantially surrounds the TIM, and a lid placed over the TIM to contact a surface thereof. Thus, a TIM can be prevented from flowing down from the original position at high temperatures. Therefore, the performance of the semiconductor package does not deteriorate even at high temperatures.

Abstract: Embodiments of the invention are directed to semiconductor die packages. One embodiment of the invention is directed to a semiconductor die package including, (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface, (c) a gate lead structure being coupled to the first surface, and (d) a molding material around the source lead structure and the semiconductor die, where the molding material exposes the second surface of the semiconductor die and the major surface of the source lead structure.

Abstract: A power semiconductor device is disclosed, which comprises a semiconductor layer including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, which are periodically formed in the lateral direction, and a power semiconductor element including the semiconductor layers that are formed periodically, wherein a distribution of an amount of an impurity in a vertical direction of the first semiconductor layer differs from a distribution of an amount of an impurity in the vertical direction of the second semiconductor layer.

Abstract: First and second IP cores are formed on one chip. Each of the first and second IP cores has metal layers. In the first IP core, an uppermost layer of the metal layers is thick and is a layer on which a core power source line is formed. In the second IP core, a metal layers equal in level to the uppermost layer in the first IP core becomes an intermediate layer. In the second IP core, thin intermediate layers are formed on this intermediate layer. Thin intermediate layers are layers on which signal lines are formed and have a narrow wiring pitch. In the second IP core, a layer on which a power source line is formed is provided on the thin intermediate layers.

Abstract: A power MOSFET layout according to one embodiment of the invention comprises a substrate and a plurality of cells. Each of the cells includes a base portion, a plurality of protruding portions extending from the base portion, and a plurality of photo-resist regions. Each of the cells is geometrically configured with the base portion and the plurality of protruding portions defining a closed cell boundary enclosing each of said cells. The cells are formed over the substrate, and the closed cell boundaries of the cells are arranged regularly with each other with no overlapping among the cells. The base portions are disposed in a matrix arrangement having rows and columns. The base portions are oriented from end to end in a direction of the columns and the protruding portions extend from the base portions along a direction of the rows. The photo-resist regions cover the base portions on the same column. None of the protruding portions are disposed between the base portions on the same column.