Patents Examined by Victor A. Mandala, Jr.
  • High voltage device and high voltage device for electrostatic discharge protection circuit
    Patent number: 7067887
    Abstract: A high voltage device for an electrostatic discharge protection circuit is provided. A silicon layer is disposed in a substrate. A first type well and a second type well are disposed in the silicon layer. A lightly doped region of a second type well is located next to the first type well. A heavily doped region of the second type well is located underneath a portion of the first type well and the lightly doped region. A gate structure is disposed over a portion of the first type well and the lightly doped region. A second type first doped region and a second type second doped region are disposed in the lightly doped region and the first type well on each side of the gate structure. An isolation structure is disposed in the lightly doped region. A first type doped region is disposed in the first type well.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: June 27, 2006
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chyh-Yih Chang, Li-Jen Hsien
  • Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and method for realizing power vertical MOS transistors with improved static and dynamic performances and high scaling down density
    Patent number: 7067363
    Abstract: A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: June 27, 2006
    Assignee: STMicroelectronics S.r.l.
    Inventors: Angelo Magri′, Ferruccio Frisina, Giuseppe Ferla, Marco Camalleri
  • Bonding pad and chip structure
    Patent number: 7064449
    Abstract: A chip structure and a bonding pad are provided. The chip structure comprises a chip and at least a bonding pad. The chip has an active surface. The bonding pad is disposed on the active surface of the chip. The bonding pad comprises a polygonal body and a plurality of first protruding portions. The polygonal body has a first planar surface and a corresponding second planar surface. The second planar surface of the polygonal body is in contact with the chip. The first protruding portions are disposed on the first planar surface at the corner regions of the polygonal body. By modifying the geometric shape of the bonding pad, the yield of bonding the chip structure and another device together through the bonding pad is increased.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: June 20, 2006
    Assignee: Himax Technologies, Inc.
    Inventors: Chiu-Shun Lin, Kuan-Chou Lin, Chia-Hui Wu, Pai-Sheng Cheng
  • SCR-ESD structures with shallow trench isolation
    Patent number: 7061051
    Abstract: A novel device structure and process are described for an SCR ESD protection device used with shallow trench isolation structures. The invention incorporates an SCR device with all SCR elements essentially contained within the same active area without STI elements being interposed between the device anode and cathode elements. This enhances ESD performance by eliminating thermal degradation effects caused by interposing STI structures, and enhances the parasitic bipolar characteristics essential to ESD event turn on. Enabling this unique design is the use of an insulation oxide surface feature which prevents the formation of contact salicides in unwanted areas. This design is especially suited to silicon-on-insulator design, as well as conventional SCR and LVTSCR designs.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: June 13, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Ta-Lee Yu
  • Light-emitting device comprising an EU(II)-activated phosphor
    Patent number: 7061024
    Abstract: The invention concerns a light emitting device comprising a light emitting structure capable of emitting primary light of a wavelength less then 480 nm and a luminescent screen comprising a phosphor of general formula (Sr1-a-bCabBacMgdZne)SixNyOz:Eua, wherein 0.002?a?0.2, 0.0?b?0.25, 0.0?c?0.25, 0.0?d?0.25, 0.0?e?0.25, 1.5?x?2.5, 1.5?y?2.5 and 1.5?z?2.5. The invention also concerns a luminescent screen comprising a phosphor of general formula (Sr1-a-bCabBacMgdZne)SixNyOz:Eua, wherein 0.002?a?0.2, 0.0?b?0.25, 0.0?c?0.25, 0.0?d?0.25, 0.0?e?0.25, 1.5?x?2.5, 1.5?y?2.5 and 1.5?z?2.5. The invention also concerns a phosphor of general formula (Sr1-a-bCabBacMgdZne)SixNyOz:Eua, wherein 0.002?a?0.2, 0.0?b?0.25, 0.0?c?0.25, 0.0?d?0.25, 0.0?e?0.25, 1.5?x?2.5, 1.5?y?2.5 and 1.5 <z<2.5.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: June 13, 2006
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Peter Schmidt, Thomas Jüstel, Walter Mayr, Hans-Dieter Bausen, Wolfgang Schnick, Henning Höppe
  • Opto-electronic component
    Patent number: 7053457
    Abstract: The invention relates to an opto-electronic component for converting electromagnetic radiation into an intensity-dependent photocurrent, comprising a substrate (1) with a microelectronic circuit whose surface is provided with a first layer (7) which is electrically contacted thereto and made of amorphous silicon a-i:H or alloys thereof, and at least one other optically active layer (8) is disposed upstream from said first layer in the direction of incident light thereof (7). The invention also relates to the production thereof. The aim of the invention is to improve upon an opto-electronic component of the above-mentioned variety in order to obtain high spectral sensitivity within the visible light range and, correspondingly, significantly reduce sensitivity to radiation in the infrared range without incurring any additional construction costs.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: May 30, 2006
    Assignee: STMicroelectronics NV
    Inventors: Peter Rieve, Jens Prima, Konstantin Seibel, Marcus Walder
  • Planarization of metal container structures
    Patent number: 7053462
    Abstract: A conductive material is provided in an opening formed in an insulative material. The process involves first forming a conductive material over at least a portion of the opening and over at least a portion of the insulative material which is outside of the opening. Next, a metal-containing fill material is formed over at least a portion of the conductive material which is inside the opening and which is also over the insulative material outside of the opening. The metal-containing material at least partially fills the opening. At least a portion of both the metal-containing fill material and the conductive material outside of the opening is then removed. Thereafter, at least a portion of the metal-containing fill material which is inside the opening is then removed.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: May 30, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Sam Yang, John M. Drynan
  • Circuit device and method of manufacturing the same
    Patent number: 7053492
    Abstract: The overflow of a brazing material (19) from a die pad (11) is prevented by forming a second plating film (14B) on the surface of the die pad (11). The second plating film (14B) is provided around the surface of the die pad 11 so as to enclose an area where a semiconductor element (13) is mounted. In a step of mounting the semiconductor element (13) on the die pad (11) with the brazing material (19), the brazing material (19) overflows from the first plating film (14A) when the semiconductor element (13) is mounted on the upper part of the molten brazing material. However, the second plating film (14B) functions as a blocking area by which the overflow of the brazing material is prevented. Therefore, a short circuit can be prevented from arising between the die pad (11) and the bonding pad (12) because of the brazing material that has spread.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: May 30, 2006
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Kouji Takahashi, Kazuhisa Kusano, Noriaki Sakamoto
  • GaN group semiconductor light-emitting element with concave and convex structures on the substrate and a production method thereof
    Patent number: 7053420
    Abstract: Concaves and convexes 1a are formed by processing the surface layer of a first layer 1, and second layer 2 having a different refractive index from the first layer is grown while burying the concaves and convexes (or first crystal 10 is grown as concaves and convexes on crystal layer S to be the base of the growth, and second crystal 20 is grown, which has a different refractive index from the first crystal). After forming these concavo-convex refractive index interfaces 1a (10a), an element structure, wherein semiconductor crystal layers containing a light-emitting layer A are laminated, is formed. As a result, the light in the lateral direction, which is generated in the light-emitting layer changes its direction by an influence of the concavo-convex refractive index interface and heads toward the outside.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: May 30, 2006
    Assignee: Mitsubishi Cable Industries, Ltd.
    Inventors: Kazuyuki Tadatomo, Hiroaki Okagawa, Yoichiro Ouchi, Takashi Tsunekawa
  • Semiconductor device having switch circuit to supply voltage
    Patent number: 7050339
    Abstract: A memory cell array has memory cells arranged in a matrix form. The memory cell includes a floating gate and a control gate. Word lines are each coupled to the control gates of the memory cells which are arranged on a corresponding one of the rows in the memory cell array. Bit lines are each coupled to drains of the memory cells which are arranged on a corresponding one of the columns in the memory cell array. An external voltage is supplied from the exterior to an external voltage input terminal. A first voltage generating circuit lowers the external voltage to generate a voltage which is to be supplied to the word line coupled to the control gates. A second voltage generating circuit lowers the external voltage to generate a voltage which is to be supplied to the bit line coupled to the drains.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: May 23, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toru Tanzawa
  • Durable electronic assembly with conductive adhesive
    Patent number: 7034403
    Abstract: An electronic assembly comprising a first electronic element, a second electronic element, and a durably flexible bond therebetween. The bond comprises an anisotropic conductive adhesive that includes elongated electrically conductive particles. The bond provides at least one electrical pathway between the first electronic element and the second electronic element through an elongated contact region. This bond is functionally maintained for at least about 200 flexes.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: April 25, 2006
    Assignee: 3M Innovative Properties Company
    Inventors: Ranjith Divigalpitiya, David A. Kanno, Patrice Jannic, Christophe Arnold, Richard Sabatier, Glen Connell
  • Biochip for the capacitive stimulation and/or detection of biological tissue and a method for its production
    Patent number: 7034371
    Abstract: The present invention relates to a biochip for capacitive stimulation and/or detection of biological tissue. The biochip includes a support structure, at least one stimulation and/or sensor device, which is arranged in or on the support structure, and at least one dielectric layer, one layer surface of which is arranged on the stimulation and/or sensor device and the opposite layer surface forms a stimulation and/or sensor surface for the capacitive stimulation and/or detection of biological tissue. The dielectric layer includes (Tix, Zr1-x)O2, with 0.99?x?0.5, or a TiO2 and ZrO2 layer arrangement.
    Type: Grant
    Filed: November 3, 2003
    Date of Patent: April 25, 2006
    Assignee: Infineon Technogies AG
    Inventors: Matthias Schreiter, Reinhard Gabl, Martin Jenkner, Björn Eversmann, Franz Hofmann
  • Device for electrostatic discharge protection
    Patent number: 7030461
    Abstract: The present invention is related to an Electrostatic Discharge protection device. This may be a semiconductor device such as a CMOS transistor, having a snap-back IV characteristic, in order to withstand ESD pulses. The device of the invention comprises an additional doped region, which influences the internal resistance of the substrate whereupon the device is built. This has a positive effect on the snap-back characteristic, putting the snap back trigger voltage and current at a lower value, compared to prior art devices.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: April 18, 2006
    Assignee: Interuniversitair Microelektronica Centrum (IMEC)
    Inventors: Vesselin K. Vassilev, Guido Groeseneken
  • Semiconductor photocathode and photoelectric tube using the same
    Patent number: 7030406
    Abstract: A semiconductor photocathode comprises a p+-type semiconductor substrate of GaSb, and a p?-type light absorbing layer of InAsSb. A p+-type hole blocking layer is formed between the substrate and the light absorbing layer having wider energy band gap than that of the light absorbing layer, the blocking layer being made of AlGaSb.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: April 18, 2006
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Tadataka Edamura, Minoru Niigaki
  • Dual-damascene process and associated floating metal structures
    Patent number: 7026235
    Abstract: In one embodiment, an interconnect line on one level of an integrated circuit is electrically coupled to another interconnect line on another level. The two layers of interconnects may be coupled together using a via. To reduce capacitance between the interconnect lines, an air core is formed between them. The air core may be formed by using a chemistry that includes a noble gas fluoride to etch a sacrificial layer between the interconnect layers.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: April 11, 2006
    Assignee: Cypress Semiconductor Corporation
    Inventors: Mira Ben-Tzur, Krishnaswamy Ramkumar
  • Semiconductor devices having a non-volatile memory transistor and methods for manufacturing the same
    Patent number: 7026685
    Abstract: Semiconductor devices including a non-volatile memory transistor and methods for manufacturing such semiconductor devices are described. One semiconductor device may include a silicon substrate 10, a floating gate 22 disposed above the silicon substrate 10 through a first dielectric layer 20, a second dielectric layer 26 that contacts at least a part of the floating gate 22, a control gate 28 formed over the second dielectric layer 26, and a source region 14 and a drain region 16 formed in the silicon substrate 10. A wiring layer 40 is provided above the floating gate 22, and the entirety of the floating gate 22 is overlapped by the wiring layer 40 as viewed in a plan view.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: April 11, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Tomoyuki Furuhata
  • Teardrop shaped lead frames
    Patent number: 7023075
    Abstract: A lead frame for use in solid state relays has a teardrop shaped frame. The frame has a small rounded portion connected to a large rounded portion. A power semiconductor is mounted in the large rounded portion. The teardrop shape eliminates sharp corners found in rectangular frames and allows heat to dissipate radially in all directions. More metal in close proximity to the power semiconductor, maintaining a lower aspect ratio of length to width, allows the semiconductor to run cooler at any given load. Several vent holes are located in the small rounded portion, which act as exhaust ports for the fumes generated in the heating stage of the solder re-flow, increasing solder coverage and improving reliability. The life of solder junctions utilizing the teardrop shaped lead frame which are subjected to temperature cycling while under load is increased, thus extending the life of the solid state relay.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: April 4, 2006
    Assignee: Crydom Technologies
    Inventors: Eugen Popescu, Herbert Otto Fredrickson
  • Semiconductor device and method of manufacturing the same
    Patent number: 7023021
    Abstract: The present invention improves the aperture ratio of a pixel of a reflection-type display device or a reflection type display device without increasing the number of masks and without using a blackmask. A pixel electrode (167) is arranged so as to partially overlap a source wiring (137) for shielding the gap between pixels from light, and a thin film transistor is arranged so as to partially overlap a gate wiring (166) for shielding a channel region of the thin film transistor from light, thereby realizing a high pixel aperture ratio.
    Type: Grant
    Filed: February 2, 2001
    Date of Patent: April 4, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Method of using a germanium layer transfer to Si for photovoltaic applications and heterostructure made thereby
    Patent number: 7019339
    Abstract: Ge/Si and other nonsilicon film heterostructures are formed by hydrogen-induced exfoliation of the Ge film which is wafer bonded to a cheaper substrate, such as Si. A thin, single-crystal layer of Ge is transferred to Si substrate. The bond at the interface of the Ge/Si heterostructures is covalent to ensure good thermal contact, mechanical strength, and to enable the formation of an ohmic contact between the Si substrate and Ge layers. To accomplish this type of bond, hydrophobic wafer bonding is used, because as the invention demonstrates the hydrogen-surface-terminating species that facilitate van der Waals bonding evolves at temperatures above 600° C. into covalent bonding in hydrophobically bound Ge/Si layer transferred systems.
    Type: Grant
    Filed: April 17, 2002
    Date of Patent: March 28, 2006
    Assignee: California Institute of Technology
    Inventors: Harry A. Atwater, Jr., James M. Zahler
  • Sidewall formation for high density polymer memory element array
    Patent number: 7015504
    Abstract: Systems and methodologies are disclosed for increasing the number of memory cells associated with a lithographic feature. The systems comprise memory elements that are formed on the sidewalls of the lithographic feature by employing various depositing and etching processes. The side wall memory cells can have a bit line of the wafer as the first electrode and operate with a second formed electrode to activate a portion of an organic matter that is formed there between.
    Type: Grant
    Filed: November 3, 2003
    Date of Patent: March 21, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christopher F. Lyons, Mark S. Chang, Sergey D. Lopatin, Ramkumar Subramanian, Patrick K. Cheung, Minh V. Ngo, Jane V. Oglesby