Abstract: There is provided a thin film transistor including an active layer on a substrate (the active layer including polysilicon and a metal catalyst dispersed in the polysilicon, a source area, a drain area, and a channel area), a gate electrode disposed on the channel area of the active layer, a source electrode electrically connected to the source area, and a drain electrode electrically connected to the drain area, wherein the gate electrode, the source area, and the drain area of the active layer include metal ions, the source area and the drain area are separate from each other, and the channel is disposed between the source area and the drain area.

Abstract: A method of manufacturing an opto-electric device is disclosed, comprising the steps of providing a substrate (10), overlying a first main side of the substrate with an electrically interconnected open shunting structure (20), embedding the electrically interconnected open shunting structure in a transparent layer (30), removing the substrate from the embedded electrically interconnected open shunting structure, depositing a functional layer structure (40) over a free surface (31) formed after removal of the substrate.

Abstract: The present invention is a method for producing a light-emitting device whose p contact layer has a p-type conduction and a reduced contact resistance with an electrode. On a p cladding layer, by MOCVD, a first p contact layer of GaN doped with Mg is formed. Subsequently, after lowering the temperature to a growth temperature of a second p contact layer being formed in the subsequent process, which is 700° C., the supply of ammonia is stopped and the carrier gas is switched from hydrogen to nitrogen. Thereby, Mg is activated in the first p contact layer, and the first p contact layer has a p-type conduction. Next, the second p contact layer of InGaN doped with Mg is formed on the first p contact layer by MOCVD using nitrogen as a carrier gas while maintaining the temperature at 700° C. which is the temperature of the previous process.

Abstract: Disclosed is a method to form a titanium nitride (TiN) hard mask in the Damascene process of forming interconnects during the fabrication of a semiconductor device, while the type and magnitude of stress carried by the TiN hard mask is controlled. The TiN hard mask is formed in a multi-layered structure where each sub-layer is formed successively by repeating a cycle of processes comprising TiN and chlorine PECVD deposition, and N2/H2 plasma gas treatment. During its formation, the stress to be carried by the TiN hard mask is controlled by controlling the number of TiN sub-layers and the plasma gas treatment duration such that the stress may counter-balance predetermined external stress anticipated on a conventionally made TiN hard mask, which causes trench sidewall distortion, trench opening shrinkage, and gap filling problem.

Abstract: The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Conductive lines such as silicon are formed over stacked nonvolatile memory structures. Word line trenches separate neighboring ones of the silicon lines. The silicon lines separated by the word line trenches are oxidized, making insulating surfaces in the word line trenches. Word lines are made in the word line trenches.

Abstract: A method of fabricating an optoelectronic integrated circuit substrate includes defining a photonic device region on a first substrate, the photonic device region having a photonic device formed thereon, forming a trench in the photonic device region on a top surface of the first substrate, the trench having a first depth, filling the trench with a dielectric, bonding a second substrate on the first substrate to cover the trench, and thinning the second substrate to a first thickness.

Abstract: A semiconductor pillar which has a first conductivity type and protrudes from a semiconductor substrate, is formed. A bottom diffusion layer having a second conductivity type is formed in the semiconductor substrate around a bottom of the semiconductor pillar. A gate insulator film which covers a side surface of the semiconductor pillar, is formed. A gate electrode which covers the gate insulator film, is formed. A top diffusion layer having the second conductivity type is formed at a top portion of the semiconductor pillar. The top diffusion layer including a semiconductor body is formed by an epitaxial growth which contains an impurity.

Abstract: A method for producing a light emitting transfer sheet includes the steps of preparing a light emitting element sheet including a light semiconductor layer connected to an electrode portion on one side surface and a phosphor layer laminated on the other side surface; dividing the light emitting element sheet into plural pieces to form a plurality of light emitting elements; disposing a plurality of the light emitting elements on a substrate to be spaced apart from each other; forming a reflecting resin layer containing a light reflecting component on the substrate so as to cover the light emitting elements; and removing the reflecting resin layer partially so that one side surface of the electrode portion is exposed from the reflecting resin layer.

Abstract: A method of thermally treating a wafer includes loading a wafer into a process chamber having one or more regions of uniform temperature gradient and one or more regions of non-uniform temperature gradient. A defect is detected in the wafer. The wafer is aligned to position the defect within one of the one or more regions of uniform temperature gradient. A rapid thermal process is performed on the wafer in the process chamber while the defect is positioned within one of the one or more regions of uniform temperature gradient.

Abstract: A target space ratio of a monitor pattern on a substrate for inspection is determined to be different from a ratio of 1:1. A range of space ratios in a library is determined to include the target space ratio and not include a space ratio of 1:1. The monitor pattern is formed on a film to be processed by performing predetermined processes on the substrate for inspection. Sizes of the monitor pattern are measured. The sizes of the monitor pattern are converted into sizes of a pattern of the film to be processed having a space ratio of 1:1, and processing conditions of the predetermined processes are compensated for based on the sizes of the converted pattern of the film to be processed. After that, the predetermined processes are performed on a wafer under the compensated conditions to form a pattern having a space ratio of 1:1 on the film to be processed.

Abstract: A wafer-level bonding method for fabricating wafer level camera lenses is disclosed. The method includes: providing a lens wafer including lenses arranged in an array and a sensor wafer including sensors arranged in an array; measuring and analyzing an FFL of each lens to obtain a corresponding FFL compensation value for each lens; forming a thin transparent film (TTF) on each sensor of the sensor wafer, and the thickness of TTF is determined by the FFL compensation value of the corresponding lens; aligning and bonding the lens wafer with the sensor wafer having TTFs formed thereon. Since the focal length of each lens is adjusted to compensate the FFL of the lens by adding a TTF of transparent optical material with an index of refraction that is similar to the index of refraction of the sensor cover glass, the FFL variation of each camera lens can be reduced.

Abstract: A wiring board provided with a silicon substrate including a through hole that communicates a first surface and a second surface of the silicon substrate. A capacitor is formed on an insulating film, which is applied to the silicon substrate, on the first surface and a wall surface defining the through hole. A capacitor part of the capacitor includes a first electrode, a dielectric layer, and a second electrode that are sequentially deposited on the insulating film on the first surface and the wall surface of the through hole. A penetration electrode is formed in the through hole covered by the first electrode, the dielectric layer, and the second electrode of the capacitor part.

Abstract: A process for fabricating a tapered field plate dielectric for high-voltage semiconductor devices is disclosed. The process may include depositing a thin layer of oxide, depositing a polysilicon hard mask, depositing a resist layer and etching a trench area, performing deep silicon trench etch, and stripping the resist layer. The process may further include repeated steps of depositing a layer of oxide and anisotropic etching of the oxide to form a tapered wall within the trench. The process may further include depositing poly and performing further processing to form the semiconductor device.

Abstract: A filler for filling a gap includes a compound represented by the following Chemical Formula 1. SiaNbOcHd.??[Chemical Formula 1] In Chemical Formula 1, a, b, c, and d represent relative amounts of Si, N, 0, and H, respectively, in the compound, 1.96<a<2.68, 1.78<b<3.21, 0?c<0.19, and 4<d<10.

Abstract: The present invention provides a manufacturing method of a power transistor device. First, a semiconductor substrate of a first conductivity type is provided, and at least one trench is formed in the semiconductor substrate. Next, the trench is filled with a dopant source layer, and a first thermal drive-in process is performed to form two doped diffusion regions of a second conductivity type in the semiconductor substrate, wherein the doping concentration of each doped diffusion region close to the trench is different from the one of each doped diffusion region far from the trench. Then, the dopant source layer is removed and a tilt-angle ion implantation process and a second thermal drive-in process are performed to adjust the doping concentration of each doped diffusion region close to the trench.

Abstract: A method for patterning an epitaxial substrate includes: (a) forming an etch mask layer over an epitaxial substrate, and patterning the etch mask layer using a patterned cover mask layer to form the etch mask layer into a plurality of spaced apart mask patterns; and (b) etching the epitaxial substrate that is exposed from the mask patterns, and removing the mask patterns such that the epitaxial substrate is formed with a plurality of spaced apart substrate patterns.

Abstract: A method of forming multiple different width dimension features simultaneously. The method includes forming multiple sidewall spacers of different widths formed from different combinations of conformal layers on different mandrels, removing the mandrels, and simultaneously transferring the pattern of the different sidewall spacers into an underlying layer.

Abstract: A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.

Abstract: Image sensor pixels are provided having junction gate photodiodes. A group of pixels may have a shared floating diffusion region and a shared source-follower transistor. The source-follower transistor may be a JFET source-follower with a gate that forms the floating diffusion region. The JFET source-follower may be a vertical or lateral JFET. A reset diode may be forward-biased to reset the floating diffusion region. Each pixel may have a JFET that serves as a charge transfer barrier between the junction gate photodiode and the floating diffusion region. The charge transfer barrier JFET may be a lateral JFET. The image sensor pixels may be formed without any metal-oxide-semiconductor devices.

Abstract: An electrical interconnect providing an interconnect between contacts on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a resilient substrate with a plurality of through holes extending from a first surface to a second surface. A resilient material is located in the through holes. The resilient material includes an opening extending from the first surface to the second surface. A plurality of discrete, free-flowing conductive nano-particles are located in the openings of the resilient material. The conductive particles are substantially free of non-conductive materials. A plurality of first contact members are located in the through holes adjacent the first surface and a plurality of second contact members are located in the through holes adjacent the second surface. The first and second contact members are electrically coupled to the nano-particles.