Abstract: A semiconductor device package includes a first substrate, a second substrate, and a first electronic component between the first substrate and the second substrate. The first electronic component has a first surface facing the first substrate and a second surface facing the second substrate. The semiconductor device package also includes a first electrical contact disposed on the first surface of the first electronic component and electrically connecting the first surface of the first electronic component with the first substrate. The semiconductor device package also includes a second electrical contact disposed on the second surface of the first electronic component and electrically connecting the second surface of the first electronic component with the second substrate. A method of manufacturing a semiconductor device package is also disclosed.

Abstract: A display apparatus includes a substrate, a pixel definition layer arranged over the substrate and including at least one opening area, and an organic emission layer arranged over the pixel definition layer and covering the opening area, wherein a center of the opening area and a center of the organic emission layer are arranged at different positions in a plan view.

Abstract: A semiconductor structure includes a first FET device, a second FET device disposed, and an isolation separating the first FET device and the second FET device. The first FET device includes a fin structure, a first work function metal layer disposed over the fin structure, and a high-k gate dielectric layer between the first work function metal layer and the fin structure. The second FET device includes a plurality of nanosheets separated from each other, a second work function metal layer surrounding each of the nanosheets, and the high-k gate dielectric layer between the second work function metal layer and each of the nanosheets. A portion of the high-k gate dielectric layer is directly over the isolation.

Abstract: A display panel includes a driving backplane, a plurality of detection pads, a light emitting function layer, and a flexible circuit board. The driving backplane has a pixel driving region and a peripheral region, and the peripheral region has bonding pads; an edge of the driving backplane is surrounded by a first section and a second section, and the bonding pads are located between the first section and the pixel driving region; a plurality of detection pads are disposed in and distributed along the second section; a light emitting function layer is disposed on the driving backplane and located in the pixel driving region; a flexible circuit board extends between the first section and the pixel driving region, and is bonded to the bonding pads; a first packaging layer is disposed on the light emitting function layer.

Abstract: A method of manufacturing a display substrate includes: forming a switch unit on a base substrate; forming a planarization layer on one side of the switch unit away from the base substrate, wherein a region, corresponding to an output electrode, of the planarization layer is provided with a planarization layer via hole, and an orthographic projection of the planarization layer via hole onto the base substrate is located within an orthographic projection region of the output electrode onto the base substrate; etching a surface of a region, corresponding to the planarization layer via hole, of the output electrode; and forming a pixel electrode on one side of the planarization layer away from the switch unit, wherein the pixel electrode is in contact with the output electrode through the planarization layer via hole.

Abstract: A display panel, a display device and a method for manufacturing a display panel are discussed. The display panel includes a display area, wherein a portion of the display area is a light sensing area that overlaps an optical sensor, and a remaining portion is a general area that does not overlap the optical sensor. The display area includes a plurality of sub-pixel areas disposed in the general area and the light sensing area, and a plurality of transmissive pixel areas disposed in a light sensing area, wherein the panel includes a general light-emissive element corresponding to the sub-pixel area of the general area and including a main light-emissive layer between first and second electrodes, and a multi light-emissive element corresponding to the sub-pixel area of the light sensing area and including a main light-emissive layer and an auxiliary light-emissive layer disposed between the first and second electrodes.

Abstract: An organic light-emitting diode (OLED) includes: a first electrode, a first light-emitting layer disposed on a side of the first electrode, a charge generation layer disposed on a side, away from the first electrode, of the first light-emitting layer, a second light-emitting layer disposed on a side, away from the first light-emitting layer, of the charge generation layer, and a second electrode disposed on a side, away from the charge generation layer, of the second light-emitting layer. The OLED further includes: a process conversion layer, disposed between the first electrode and the second electrode, and configured to fill an uneven region between the first electrode and the second electrode.

Abstract: A display device includes a display panel including a plurality of light emitting areas; and an input sensor disposed on the display panel and having a first conductive layer and a first insulating layer disposed on the first conductive layer. The first insulating layer includes a plurality of optical patterns that extend in a direction away from the first conductive layer.

Abstract: A display panel, comprising a plurality of sub-pixels of at least one color provided corresponding to a display area. The peripheral sub-pixels of the sub-pixels provided along the edge of the display area are edge sub-pixels, and the remaining sub-pixels surrounded by the edge sub-pixels and located in the display area are internal sub-pixels; a portion of the plurality of sub-pixels in the display area is a display pixel portion, and the edge contour of the display pixel portion is formed by the edge sub-pixels; the shape of the edge sub-pixels in the plurality of sub-pixels is different from that of the internal sub-pixels of the same color; the edge sub-pixels in the plurality of sub-pixels fill an area between the internal sub-pixels and the edge of the display area, so that the edge contour shape of the display pixel portion is consistent with that of the display area.

Abstract: Described is a thin film transistor which comprises: a dielectric comprising a dielectric material; a first structure adjacent to the dielectric, the first structure comprising a first material; a second structure adjacent to the first structure, the second structure comprising a second material wherein the second material is doped; a second dielectric adjacent to the second structure; a gate comprising a metal adjacent to the second dielectric; a spacer partially adjacent to the gate and the second dielectric; and a contact adjacent to the spacer.

Abstract: Display substrate, display device, high-precision metal mask are provided. Display substrate includes: first, second, and third sub-pixels; in first direction, first and third sub-pixels are alternately arranged to form first sub-pixel rows, second sub-pixels form second sub-pixel rows; in second direction, first and second sub-pixel rows are alternately arranged; two first and two third sub-pixels in two adjacent rows and two adjacent columns form 2*2 array; in the array, two first sub-pixels are in different rows and in different columns, so are the two third sub-pixels, connection lines of centers of two first and two third sub-pixels form virtual quadrilateral, second sub-pixel is within virtual quadrilateral; for multiple distances from centers of two first and two third sub-pixels corresponding to same virtual quadrilateral to center of second sub-pixel, at least two distances are different. Brightness centers of virtual pixels have more uniform distribution.

Abstract: The present disclosure discloses a silicon-based nanowire, a preparation method thereof, and a thin film transistor. By using a eutectic point of catalyst particles and silicon, and a driving factor that the Gibbs free energy of amorphous silicon is greater than that of crystalline silicon, and due to absorption of the amorphous silicon by the molten catalyst particles to form a supersaturated silicon eutectoid, the silicon nucleates and grows into silicon-based nanowires. Moreover, during the growth of the silicon-based nanowire, the amorphous silicon film grows linearly along guide slots under the action of the catalyst particles, and reverse growth of the silicon-based nanowire is restricted by the retaining walls, thus obtaining silicon-based nanowires with a high density and high uniformity. Furthermore, by controlling the size of the catalyst particles and the thickness of the amorphous silicon film, the width of the silicon-based nanowire may also be controlled.

Abstract: The present disclosure provides a method for fabricating a displaying backplane, a displaying backplane and a displaying device, and relates to the technical field of displaying. The method includes forming a first active layer and a second active layer on a substrate base plate; forming a first grid insulating layer covering the first active layer and the second active layer; forming a first grid on the first grid insulating layer; performing ion implantation to the first no-channel regions, the second no-channel regions and the second channel region, to reduce oxygen-vacancy concentrations of the first no-channel regions, the second no-channel regions and the second channel region; and forming a second grid on the first grid insulating layer.

Abstract: A display substrate has a plurality of sub-pixel regions used to display images and a non-sub-pixel region surrounding the sub-pixel regions. The display substrate includes a light-emitting device layer. The light-emitting device layer includes a first electrode layer. The first electrode includes a plurality of first electrodes electrically connected to each other and at least one hollowed-out region among part of adjacent first electrodes. The at least one hollowed-out region is located in the non-sub-pixel region.

Abstract: A display device is disclosed that includes: a substrate comprising a display area and a component area including a transmission area; a first thin-film transistor comprising a first semiconductor layer and a first gate electrode, the first semiconductor layer including a silicon semiconductor; a first insulating layer covering the first gate electrode; a second thin-film transistor comprising a second semiconductor layer arranged on the first insulating layer and a second gate electrode, the second semiconductor layer including an oxide semiconductor; a second insulating layer covering the second gate electrode and having a transmission hole overlapping the transmission area; an intermediate insulating layer between the first insulating layer and the second insulating layer; a conductive pattern between the intermediate insulating layer and the first insulating layer; and a display element arranged on the second insulating layer, wherein the transmission hole exposes an upper surface of the intermediate insu

Abstract: A display panel includes an under screen camera display area and a normal display area surrounding the under screen camera display area, a plurality of switch assemblies are positioned at the normal display area, and a plurality of sub-pixels are positioned at the under screen camera display area. The display panel includes an insulating layer group and a plurality of connection lines; a plurality of trenches are positioned on the insulating layer group and extend from the sub-pixels to the switch assemblies; and at least part of the connection lines is positioned in the trench to reduce spacing distance between two adjacent connection lines, where the connection lines are connected between the switch assemblies and the sub-pixels.

Abstract: There is provided a pixel array including a plurality of sub-pixels, which include first sub-pixels, second sub-pixels, and third sub-pixels. The first and third sub-pixels are alternately arranged along a row direction and form a plurality of first pixel rows, the first and third sub-pixels, which are in a same column, in the plurality of first pixel rows are alternately arranged, and the second sub-pixels are arranged along the row direction and form second pixel rows. Lines sequentially connecting centers of any two of the first sub-pixels and any two of the third sub-pixels, which are arranged in an array, together form a first virtual quadrilateral, and one of the second sub-pixels is in each first virtual quadrilateral. At least one interior angle of the first virtual quadrilateral is not 90°. At least one of the first, second and third sub-pixels has a corner circularly or rectilinearly chamfered.

Abstract: A display device includes: a substrate comprising a first display area and a second display area, the first display area comprising a transparent area and the second display area being arranged to surround at least a portion of the first display area; a first pixel in the first display area and comprising a first pixel electrode, a first intermediate layer, and a first opposite electrode; and a second pixel in the second display area and comprising a second pixel electrode, a second intermediate layer, and a second opposite electrode, wherein each of the first intermediate layer and the second intermediate layer comprises a first section having a portion where a thickness thereof is constant and a second section where the thickness thereof is variable.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

Abstract: Various gate all-around field effect transistors (GAAFET) including quantum-based features are disclosed. GAAFET may include a center core including a first end and a second end, a source region positioned circumferentially around the first end of the center core, and a drain region positioned circumferentially around the second end of the center core. The drain region may also be positioned axially opposite the source region. The GAAFET may also include a gate portion axially positioned between the source region and the drain region. The gate portion may include at least one quantum-based feature circumferentially disposed around the center core, and a gate contact circumferentially disposed around the quantum-based feature(s). The quantum-based feature(s) may include a plurality of quantum dots (QD) or at least one quantum well channel.