Abstract: The system and method improves Electronic Design Automation practices by creating a data template representing pins, elements, and dependencies for numerous components in the same functional class. A pin having the same function is represented once on the data template even if the pin name is different. Sequences of component pins having the same function are combined and are represented by a single pin on the data template. The performance of functional logic symbol generation systems increases significantly because the data template enables the creation of functional logic symbols to be accomplished quickly, accurately, and consistently.

Abstract: A device extractor for extracting devices from a hierarchical cell design. The device extractor selects a cell from the lowest level of the hierarchy and searches the cell for the device components. The device extractor searches each cell in the lowest level and then selects a "parent" cell in the penultimate level. The parent cell, and all of the children cells of the parent cell, are searched. The selection and search process continues until all of the components of the device are identified in a cell or the children cell of the cell and a proper relationship between the components is determined. The components of the identified device are masked so that they are not identified and associated with another device during subsequent searches.

Abstract: A system for interactive design and simulation of an electronic circuit allowing a user to design a circuit by graphical entry and to view full or partial simulation and design results simultaneously, on a single display window. The user is able to define the form of a display of speed, delay, loading, symbols, simulation input and/or output values on each node and any path of the design. Simulation may be user-defined or other process time. The user is further able to view any information relevant to any object in the design at any level of design abstraction, and is able to view multiple levels of design abstraction simultaneously and to display information common to the various representations.

Abstract: A method for developing computer animation using dynamics analysis comprises analyzing the basic motions of a moving body such as a human or animal body and inputting the force or torque exerted on each joint into a database, dividing each body segment from other body segments and calculating the movements of the segments by applying dynamic equations, checking constraints including the articulation of the moving body and the range of movements of the joint, calculating motions and forces produced by the restraints by applying the inverse dynamics, calculating the movements of individual segments by applying dynamic equations to develop new motions, checking restraints including the articulation of the moving body and the range of movements of each joint, calculating the motions and forces due to the restraints by inverse dynamics, and displaying the motions and forces.

Abstract: An emulation device (11) distributes common control information (8801) to each of a plurality of clock domains (1213, 1215, 1217) into which the emulation device is partitioned, and also provides the clock domains with individualized clock control (8905, 8907, 8913).

Abstract: A method and on-chip architecture are disclosed for multiplexing signals from selected external interconnect buses to chip internal buses such that bus rerouting can be implemented programmably without substantially affecting timing relations between time-parallel signals of a rerouted bus. An on-chip switch matrix is provided having N input lines crossing with M output lines to provide N times M crosspoints. A plurality of substantially less than N times M programmable interconnect switches (PIP's) are distributed symmetrically among the N.multidot.M crosspoints such that a same first number of interconnect switches (PIP's) are found along each of the N input lines thereby providing equal loading on each input line. The plurality of programmable interconnect switches (PIP's) are further distributed among the N.multidot.M crosspoints such that a same second number of interconnect switches (PIP's) are found along each of the M output lines thereby providing equal loading on each output line.

Abstract: A system and method for entering a circuit design into a computer using a schematic capture package. The schematic capture package is modified to include a library of state flow components represented by symbols which can be connected to produce a desired representation of the circuit design. The system allows a circuit design to be displayed on a video terminal using both state flow diagram and the schematic diagram symbols, with terminals of the state flow symbols connecting to terminals of the schematic symbols. The state flow diagram using state flow symbols is combined with a schematic diagram including schematic symbols to generate a netlist representing the combined circuit.

Abstract: A method for predicting circuit interconnect delays in circuits of the type that have a driving device attached to an input node of a network having a plurality of nodes, with the driving device changing states from time to time so as to impose on the network a voltage different from the previous voltage of the network. The method includes the steps of estimating the waveform on the input node and predicting the waveforms on other nodes of the network on the basis of the estimated input node waveform.

Abstract: Dynamically reconfiguring a space-based data processing system receiving data from infrared detectors, generally comprises selectively processing data based upon evaluations of prior data. The method includes communicating a first portion of unprocessed data from storage to an on-focal-plane data processor for processing, and communicating a second portion of data from storage to an off-focal-plane data processor for processing. Then, the first processed data is sent to the off-focal-plane data processor, and an evaluation of all the processed data takes place. Commands are generated to modify the content of the second portion of unprocessed data. The data "pass-through" accommodates the progressive evolution of algorithms for the on-focal-plane data processor.

Abstract: A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.

Abstract: In a system and method for controlling actuation of a vehicle passenger safety device, wherein a first time-varying measure m.sub.1 (t), itself a function of received vehicle acceleration information, is accumulated to obtain a second time-varying measure m.sub.2 (t) for subsequent comparison with a threshold value therefor, the first measure m.sub.1 (t) is "damped" prior to accumulation by subtracting therefrom a correction value or "damping factor f.sub.d." The damping factor f.sub.d may be either a constant or a time-varying function f.sub.d (t) of one or more other time-varying measures, themselves based on received vehicle acceleration information.

Abstract: An information model based on a physical system, such as the physical equipment in a power system. An object-oriented information model provides a generic power system model that may be applied to any of several specific applications. In the invention, physical pieces of equipment are represented as objects with attributes that can be verified (primary data) and relations including connectivity, grouping, and location. The model handles all known configurations of power systems and is extensible to new configurations. Attribute input is supported from primary sources and is used to calculate data required by applications programs. A window-based graphical user interface uniquely simplifies operation of the database. Thus, the present invention provides a single, easy to use, source for all proprietary application databases at a utility.

Abstract: With respect to each bit of a multiplier factor, it is judged whether or not the multiplier factor is a variable or a constant. If the multiplier factor is a constant, it is judged whether or not a bit of concern in the multiplier factor has the value of 1. Only if the bit of concern in the multiplier factor is 1, there is generated a circuit for outputting, as a partial product, a signal indicating a multiplicand. The signal indicating the multiplicand is then shifted by one bit so that the resulting signal is newly set as the signal indicating the multiplicand. By repeatedly executing the foregoing process with respect to all the bits of the multiplier factor, a circuit for calculating a partial product with respect to each bit of the multiplier factor is generated.

Abstract: A system for controllably sensing, recording, and selectively displaying data associated with operational characteristics of a vehicle is described. A plurality of transducers are connected to a programmable logic device along with data entry, data storage, and data display devices. Information received from the transducers is processed by the logic device to determine whether a certain operational characteristic has occurred during the time that certain other characteristics are present. In addition, the amount of time that the particular characteristic occurs is determined.

Abstract: A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure.

Abstract: The current invention considers automatic synthesis of segmented channel architecture of row-based FPGAs so as to achieve maximum routability and performance. The routability of a channel and the performance of the routed nets may have conflicting requirements. For a given number of tracks, very short segments usually enhance routability at the expense of performance. For such a granular segmented channel architecture routing of long nets may require that several short segments be joined together by programming horizontal antifuses. Depending on the antifuse technology, the programmed antifuses can add considerably to the path delays. A simulated annealing based channel architecture synthesis algorithm has been developed which enhances routability and performance. The synthesis algorithm is based on the fact that a strong correlation between the spatial distribution of nets and segments in a channel improves both routability and performance.

Abstract: A method and apparatus to model the power network of a VLSI circuit is described. The method includes the step of extracting the power network associated with a semiconductor circuit layout. A compacted power network is then derived from the power network. The compacted power network includes a compacted primary resistive network to characterize the electrical resistance of the power trunks within the semiconductor circuit layout. The compacted power network also includes a compacted secondary resistive network to characterize the electrical resistance of power straps that deliver power to transistors within the semiconductor circuit layout. The compacted power network constitutes a network of compaction component values that correspond to functional regions in the semiconductor circuit layout. Each of the compaction component values includes an associated set of spacial compaction values that characterize the total resistance of a functional region.

Abstract: A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing of signals between the CLB's and IOB's. Each CLB includes an internal clock selector for selecting a CLB-internal clock and at least one register that is responsive to the selected CLB-internal clock. The configurable interconnect network includes clock-carrying longlines extending in different directions past each CLB for broadcasting clock signals. The broadcast clock signals can originate outside the programmable integrated circuit or such broadcast clock signals can be generated within one or more of the CLB's and thereafter broadcast by way of the clock broadcasting longlines to others of the CLB's.

Abstract: In a printed circuit board having a plural number of conductor layers separated by a plural number of insulator layers, a Faraday cage is constructed including a first and a second ground plane disposed in a first and second conductor layer respectively. The ground planes being electrically interconnected at their peripheries, preferably by a plurality of vias. A third conductor layer is disposed between the first and second conductor layers in which a plurality of signal paths are defined. The Faraday cage surrounds a shielded portion of the third conductor layer so that electrical signals conducted through the shielded portion are isolated from electrical noise.

Abstract: A method and system for verifying design constraints on printed circuit boards and multichip modules provides for user programmability and design of new constraints and applicable verification procedures for verifying the constraints. New constraints are defined, identifying various attributes dealing with the circuit elements to which the constraint is applied, and precedence of the constraint with respect to existing constraints on circuit element. A verification procedure is defined for the constraint, and the verification procedure is registered in a constraint verification library such that it can be retrieved when an circuit element is supplied to a verification engine for verification of applicable design constraints on the circuit element.