Abstract: It is a purpose of the present invention to connect the operation of the driving-force distributing device with the operation of the driving-force reducing device at an appropriate timing to insure a stable performance of the vehicle. When a slip rate exceeds a predetermined value, a driving-force distributing device which includes a variable differential operation limiting device is first operated so as to hold a differential operation limiting torque at a predetermined value. If the slip rate further increases, a driving-force reducing device which includes a traction control device is operated so as to hold the engine output at a predetermined value. At that time, if slip rates of both racing inner wheel and racing outer wheel are further increased, the driving-force reducing device is operated to reduce the engine output.

Abstract: A clutch slip control device includes: a slip revolution speed detecting circuit for detecting an actual slip revolution speed of a clutch; a memory unit for storing constants set to satisfy response and stability of a feedback control system of the slip conditions, the constants being determined by a high-order function approximating variation in input-output frequency characteristics of a plant input for actuating the clutch and the actual slip revolution speed; a first calculation circuit for calculating a first parameter using the constants stored in the memory unit, the first parameter discretely reflecting past data of the plant input, which are obtained in a current feedback control cycle through in a cycle executed a plurality of times before; a second calculation circuit for calculating a second parameter using the constants stored in the memory unit, the second parameter discretely reflecting past data of a deviation of the actual slip revolution speed from a target slip revolution speed, which are

Abstract: A flip-flop-based circuit architecture generates a hazard-free asynchronous signal given the SET and RESET sum-of-product (SOP) solutions to an asynchronous process. The flip-flop SET and RESET SOP solutions can be hazardous. Thus, general purpose synchronous optimization tools (which are indifferent to hazards) can be used to derive the optimal SOP solutions. A fixed layer built around the SOP cores eliminates all hazards in the circuit. In one embodiment, the architecture is optimized by eliminating an RS latch and delay lines in the SOP cores. The architecture of the present invention is guaranteed to admit any semi-modular race-free state graph representation of an asynchronous process that satisfies the n-shot requirement. The state graph representations can be examined to determine if alternate, solution-specific, simplified architectures can be employed that further decrease the final area by the elimination of flip-flops or the elimination of a timing delay.

Abstract: A system for connecting signal wires between circuitry of a Field Programmable Gate Array (FPGA). When a connection cannot be made, the system attempts to move the circuitry to a different location in order to resolve the congestion. The system first attempts to move the circuitry to a different location at the same allocation level within the FPGA, and if the system is unsuccessful, it will then attempt to move all the circuitry at the allocation level of the circuitry causing the congestion to a new location within a next higher allocation level. This will continue until the top level is reached. When attempting to move the circuitry, the system first tries to place the circuitry in the closest area on one side or the other of the circuitry and then moves alternatingly outward away from the circuitry trying to find a suitable location.

Abstract: The present invention provides a method of computing the cost of a proposed clock tree change in the context of a clock skew optimization routine. According to the present invention, a recalculation of the clock skew cost due to a proposed change in the clock tree can be done without having to recompute the effect of the change to all of the sinks of that clock tree. The method stores the effects of past delay changes as unpropagated incremental changes until future changes make it necessary to propagate those changes. Thus, in this method only the parameters of the ancestors of the delayed node need to be recalculated to determine the cost of a proposed change in the clock tree. Not having to recalculate the rest of the tree greatly reduces the computational complexity and time required for the process, allowing the required iterations to be completed in a much shorter time period.

Abstract: A method for performing optical proximity correction is disclosed that not only limits the optical proximity correction to electrically relevant structures, but also improves the accuracy of the corrections by processing individual feature edges, and minimizes the mask manufacturing impacts by avoiding the introduction of jogs into the design. Critical edge regions of the relevant electrical structures are analyzed, sorted and manipulated to receive optical proximity corrections.

Abstract: An electrical circuit board (100) includes a substrate (101) on which a metallized bar code pattern (104) is disposed. The substrate (101) further includes an electrical circuit metallization pattern (103) which incorporates at least a portion of the metallized bar code pattern (104).

Abstract: A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and an interconnect network for providing program-defined routing of signals between the CLB's and IOB's. The interconnect network includes direct connect means for providing programmably-selectable, dedicated connections between a first CLB and one or more adjacent CLBs and further between a first CLB and one or more CLBs. The interconnect network also includes peripheral direct connect means for providing programmably-selectable, dedicated connections between a first configurable IOB and first and second CLBs.

Abstract: A schematic modifier editor that works in concert with a shapes modifier editor so that changes to a design layout are reflected in the schematic. The shapes modifier editor tracks the changes made to the cell hierarchy and saves the changes to a list file. The schematic modifier editor processes the list file and edits the schematic file so that its cell hierarchy corresponds with that of the modified shapes file. The modified schematic file and modified shapes file can then be compared by a conventional verification program to ensure that the modified shapes file implements the desired circuit.

Abstract: A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERQGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.

Abstract: The present invention discloses an improved wiring method. Grids are defined at a grid-routing step in such a way that a part of predetermined design criteria are met. Wiring routes are decided on the basis of these grids so that they follow the design criteria and plural functional blocks are connected together. When some nets are left in such a manner that they are assigned no wiring routes, their wiring routes are decided at a non grid-routing step following the design criteria, in defiance of the grids but in accordance with the design criteria. If there are still some nets without wiring routes, their wiring routes are decided at a non grid-routing step ignoring the design criteria. Then, some of the already-defined wiring routes are shoved so as to meet each of the design criteria, and individual wiring patters are generated with respect to all of the decided wiring routes in such a manner that the criteria are met.

Abstract: Described is an invention that provides an efficient selection of timing statements for a logic cell in response to cell pin activity when such cell is implemented as one or more instances of simulator primitives. It does so by defining a first storage structure coupled with a logic processor coupled, in turn to a second storage structure. First storage structure defines plural bitfield arrays corresponding with a cell pin and a possible logic level or state, each bitfield array having an entry for an old or a former state of the pin, a next or new state of that pin and a stable state of that pin and each bitfield array defining an index to one or more memory-based look-up tables defining the number of a timing and/or constraint parameter for the given pin of the logic cell. Such timing parameters describe a delay between two pins of the cell, while such constraint parameters describe timing constraints for the logic cell such as setup times, hold times and minimum pulse width times.

Abstract: A "no select state" is implemented with self-resetting CMOS logic circuitry so as to essentially disable the resetting function of this logic circuitry when the logic circuitry is in an idle state. As an example, within a multiplier circuit in a processor, the selection inputs to a multiplexor circuit are de-selected when there is no need for the multiplier circuitry.

Abstract: An electronic device includes an electronic circuit having points for introducing power supply voltage, ground return, and at least one output. A keyless device package holds the electronic circuit, and the keyless device package is subject to misorientation. Terminals, including terminals for power supply voltage, the ground return and the output, are connected to the electronic circuit and secured to the device package. The terminals are distributed on the device package so that a turning reorientation of the entire electronic device translates the terminals to each other only in a way which prevents electrical stress to the electronic circuit due to possible misorientation of the electronic device under test. Other devices, systems and methods are also disclosed.

Abstract: A system and a method for designing, fabricating and testing multiple cell test structures validate a cell library. Each test structure includes a plurality of logic layers where outputs of a logic layer are connected only to the inputs of a succeeding logic layer. In contrast to the conventional design method, mismatches in each logic layer are increased to assure extreme conditions in the test structure. For each logic layer, the number of fan-outs of each output from the previous logic layer is specified, and the number of basic cells in each layer is based on the number of inputs of the test structure. Based on D-optimality and maximum fan-in resolution, an assignment for connecting each fan-out and each fan-in is determined. Alternatively, a design repair algorithm can be used to make such an assignment. Each output of each logic cell in the logic layer is then assigned a length using D-optimality.

Abstract: An emulator dedicated one-chip microcomputer which can emulate without making any malfunction or without being subject to influences of noise even at low voltage, for example, when line voltage is about 1.8V, which is equipped with a level shifter 25 for converting the voltage level of signals given from the internal circuit bus 10 to the output circuit 4 from the voltage level of the external power supply VCC to the voltage level of the emulator power supply VCCA when the external power supply VCC and the emulator power supply VCCA equivalent to the voltage level at which the emulator 2 operates are supplied and an output circuit 4 outputs signals on the internal circuit bus 10 to the emulator 2 via a plurality of signal lines 7, 8, 9, and which is configured to allow the output circuit 4 to operate when the emulator power supply VCCA is supplied.

Abstract: A method for a logic optimization in a logic synthesis comprises the following steps. Prior to an actual execution of a logic flattening process, a scale of unoptimized circuits is estimated assuming that the unoptimized circuits have already been subjected to the logical flattening. The unoptimized circuits are subjected to a two-level logic optimization only when an estimated scale of the unoptimized circuits exceeds a predetermined threshold value. Prior to an actual execution of a logic flattening process, a scale of the optimized circuits is estimated assuming that the optimized circuits have already been subjected to the logic flattening. The optimized circuits are subjected to the logic flattening if an estimated scale of the optimized circuits does not exceed the predetermined threshold value.

Abstract: The invention provides an easy-to-use method of containing consistent growth and yield values at varying levels of resolution (stand, size-class) for loblolly pine plantations in the southern United States. The invention is able to make projections of estimated values using either existing stand data, or predicted from bare-ground conditions. The invention evaluates stand performance based on estimates of potential or "target" productivity yields. The invention provides long-term expected yields for strategic planning, and short term projections for inventory purposes. The invention can function as a simulation tool to provide insights into the life-cycle of a stand under varying initial conditions. While most growth and yield models use an empirical, multiple regression, "best fits to the data" modelling methodology, the present invention is based upon a biomathematical modelling concept.

Abstract: A method for deriving a two-dimensional first-range data model at a distance, d, from a two-dimensional second-range data model at a distance, d.sub.0. The method (10) comprises the steps of first smoothing the second-range data model, I, by masking the second-range data model by a masking matrix (step 24) and next undersampling the smoothed second-range data model (step 26) to yield a first-range data model. Both steps for smoothing (step 24) and undersampling (step 26) use operators depending on the ratio of the first-range distance, d, to the second-range distance, d.sub.0. One aspect of the invention includes a distance relating system (80) that performs the smoothing step (step 24) and undersampling step (step 26) to generate first-range data models from second-range data models in an intelligent sensor system.

Abstract: A method for generating a validated measurement of a process parameter at a point in time by using a plurality of individual sensor inputs from a scan of said sensors at said point in time. The sensor inputs from said scan are stored and a first validation pass is initiated by computing an initial average of all stored sensor inputs. Each sensor input is deviation checked by comparing each input including a preset tolerance against the initial average input. If the first deviation check is unsatisfactory, the sensor which produced the unsatisfactory input is flagged as suspect. It is then determined whether at least two of the inputs have not been flagged as suspect and are therefore considered good inputs. If two or more inputs are good, a second validation pass is initiated by computing a second average of all the good sensor inputs, and deviation checking the good inputs by comparing each good input including a present tolerance against the second average.