Abstract: In a semiconductor integrated circuit including a plurality of functional cells, it is determined whether or not each of the functional cells includes terminals to be electrically connected to each other. If a functional cell includes one of such terminals, a preset routing prohibiting area is set in the functional cell. If a functional cell does not include any of such terminals, a routing prohibiting area is set in the entirety of the functional cell. Then, routing between the terminals is carried out in accordance with the routing prohibiting areas.

Abstract: A navigation apparatus includes a road data memory (16) for storing therein road data of position and shape data at every road, a road map making device (14) for making road map data by reading road data of a predetermined scope from the memory device (16), a route selecting device (14) for selecting a route on a road indicated by road map data for destination, and a video signal generating device (17) for generating a video signal for displaying a road map under the condition that symbols indicating the route selected by the route selecting device (14) are superimposed upon the road map data made by the road map making device (14), wherein shape data of minor roads existing at an intersecting point of roads are used as road data stored in the memory (16). The navigation apparatus can display a route at a crossing of complicated shape more accurately in conformity with the actual route.

Abstract: An electronic device includes an electronic circuit having points for introducing power supply voltage, ground return, and at least one output. A keyless device package holds the electronic circuit, and the keyless device package is subject to misorientation. Terminals, including terminals for power supply voltage, the ground return and the output, are connected to the electronic circuit and secured to the device package. The terminals are distributed on the device package so that a turning reorientation of the entire electronic device translates the terminals to each other only in a way which prevents electrical stress to the electronic circuit due to possible misorientation of the electronic device under test. Other devices, systems and methods are also disclosed.

Abstract: The method implements implicit sequential behavior using a general finite state machine architecture (FSM) through the systematic evaluation of control flow graphs (CFGs) having one or more weight statements which are sensitive to the same unique clock edge. Each of the weight statements contained in the CFG are assigned a state in the state machine. All of the executable paths between each weight statement are fully evaluated on a node-by-node basis. From this evaluation process, expressions are extracted which define combinational logic necessary to produce additional inputs to the FSM to produce the next state, as well as expressions representing outputs of the FSM as associated with each transition from one state to another. The method also deals with proper evaluation of unrollable loops.

Abstract: A method is provided to remove redundancies in multi-level logic networks caused by reconverging signals at Boolean sum and product nodes. Generally, sum and product nodes which have potential redundancies are first identified. For each reconvergent signal at each of the nodes, it is determined whether it introduces redundancies using nondestructive Boolean analysis. No two-level expansion is made of the logic network. Moreover, for each confirmed redundancy, a redundant term is identified using Boolean analysis. Finally, the redundancy is removed, if desirable.

Abstract: An arrangement (apparatus and method) for dynamically provisioning infrastructure components in a digital communication network using an object-oriented relational paradigm. A network configuration system, also referred to as a video support system, stores all related information on each of the infrastructure components (IFCs) as objects in an object oriented relational database, including the functions, capabilities, locations, when and how the IFCs are assigned, and the capacities, working and spare, existing in and between various locations. The objects are arranged into clusters based on common characteristics, and the object clusters (modules), selectively access other modules to provide functional and logical connections independent from nonrelevant objects, such as physical location. Entity relationships establish the relevancy of different objects and object clusters.

Abstract: The present invention is a computer-based method and apparatus for constructing all-hexahedral finite element meshes for finite element analysis. The present invention begins with a three-dimensional geometry and an all-quadrilateral surface mesh, then constructs hexahedral element connectivity from the outer boundary inward, and then resolves invalid connectivity. The result of the present invention is a complete representation of hex mesh connectivity only; actual mesh node locations are determined later. The basic method of the present invention comprises the step of forming hexahedral elements by making crossings of entities referred to as "whisker chords." This step, combined with a seaming operation in space, is shown to be sufficient for meshing simple block problems. Entities that appear when meshing more complex geometries, namely blind chords, merged sheets, and self-intersecting chords, are described.

Abstract: A power analysis tool includes a power arc identifier that extracts power arc information from simulation results including the occurrence time of each arc. These occurrence times are then stored in an arc occurrence database on which power analysis can be performed after the simulation has occurred. This allows a user to specify different circuit groupings on which to perform power analysis without requiring the circuit to be resimulated. The tool also includes a power calculator that converts average current, propagation delay, and intrinsic delay stored in a power data library into positive load current and negative load current for a cell. From these currents an "internal cell" current is derived which is related to the two load currents by a formula.

Abstract: A sizing apparatus for active devices of an integrated circuit has a storage unit for storing information about connections between the active devices and a delay constraint, a size initializing unit for initializing a size of the active device to a minimum value, an electric current consumption change rate arithmetic unit for calculating a change rate of an electric current or power consumption when the size is increased, a delay calculating unit for calculating a maximum signal delay by analyzing a timing on the basis of the connecting formation, a delay constraint judging unit for judging whether or not a maximum signal delay satisfies the delay constraint, a critical path extracting unit for extracting a critical path from paths that do not satisfy the delay constraint, a delay improvement arithmetic unit for calculating an improvement rate of the signal delay of the critical path with respect to a variation quantity of the electric current or power consumption when increasing the size of the active devic

Abstract: A logic circuit partitioning system includes a logic circuit network generating portion for inputting a logical expression group and generating a logic circuit network, in which each node corresponds to each logical expression and each branch corresponds to a relationship between each logical expression, a matrix generating portion inputting the generated logical circuit network and generating a matrix, in which each row corresponds to the node in the logical circuit network and each column corresponds to an input of the logical circuit and node, and an arbitrary value is given for each element in the column corresponding to the input for the node corresponding to each row, a matrix partitioning portion for inputting the generated matrix and extracting a partial matrix which has sized in row and column greater than or equal to two and the arbitrary value at every elements therein from the matrix from the matrix generating portion, and a logic circuit network partitioning portion for partitioning partial circu

Abstract: A computer software system for modeling a process capability on a computer is provided. The computer software system comprises an operation model type for defining a plurality of operation models (33, 36, 44, 52 and 57). Each operation model represents an activity that can be performed by a process. A resource model type is for defining a plurality of resource models (32, 38, 40, 46, 48, 54, 56 and 58). Each resource model represents capacity available for use in performing an activity and rules for allocating capacity to the activity. A buffer model type is for defining a plurality of buffer models (34, 42, 50, and 60). Each buffer model represents rules for controlling a flow of material between activities. The operation model type, buffer model type, and resource model type each comprise a plurality of fields defining attributes that include a plurality of extension selector fields. Defined operation models, buffer models, and resource models are stored as nodes in an interrelated process network model.

Abstract: An automated method and system for designing an integrated circuit are disclosed which construct an initial substrate layout of the integrated circuit in response to receipt of a high-level functional description of an integrated circuit. The initial substrate layout, which includes a number of subcircuits electrically connected by a number of interconnects, is constructed based upon estimated timing characteristics of the subcircuits. Next, particular subcircuits are arranged to optimize performance of the substrate layout of the integrated circuit. Performance characteristics of the substrate layout, including timing characteristics of the number of subcircuits and resistive and capacitive characteristics of the number of interconnects, are then determined. In response to a determination of the performance characteristics of the substrate layout, operating power levels of selected subcircuits and resistances of selected interconnects are adjusted to optimize performance of the substrate layout.

Abstract: For manufacturing an integrated circuit, the production of a design for the circuit that comprises a plurality of MOS transistors is controlled by employment of a circuit simulator. ##EQU1## are calculated in the circuit simulator for the terminal nodes of the MOS transistors upon prescription of the voltages between gate and source V.sub.gs, between drain and source V.sub.ds, and between the substrate and source V.sub.bs in a consistent transistor model wherein drift, diffusion and short-channel effects are taken into consideration.

Abstract: A system and procedure for placement optimization of input/output ports associated with edges of circuit blocks within an integrated circuit design. The integrated circuit design is composed of circuit blocks that communicate using inter-block signal wires coupled to input/output ports (IOPs) located along edges of circuit blocks. An arbitrary IOP placement is first received, e.g., from a global floorplanner, and indicates (1) the allowable edge placement domains for each IOP and can optionally include (2) an arbitrary IOP placement within these allowable edge domains. A cell placer (e.g., a quadratic based standard cell placer) receives the arbitrary IOP placement and, for each circuit block, places cells represented within internal netlists. The placer does not optimize the placement of the IOPs. For each IOP, the set of cells of the net that is coupled to the IOP is determined.

Abstract: Packaged signal routing circuits (e.g. on printed circuit cards or boards), route pulse signals with very short rise times from a lossy driver to multiple devices. In these routing circuits, a complex network of conductors branches from a common junction adjacent the driver output into multiple conduction paths of unequal length. In accordance with the invention, the internal impedance of the driver is matched to the aggregate characteristic impedance of the branch paths, and a lossless compensating circuit is attached to a shortest branch path. The compensating circuit is designed to transfer signal reflections of predetermined form to the branching junction at the driver via the shortest branch.

Abstract: The invention provides a path analyzing displaying apparatus for designing a logic circuit which can achieve reduction in intervention degree of a designer and expansion of human interface with a minimum portion which requires intervention. The apparatus comprises a graphic screen for displaying information necessary for path analysis of a logic circuit of an object of designing. Logic circuit components are grouped into a target group including a noticed point determined based on a logical simulation output result and any of the logic circuit components which can have an influence on the noticed point and a non-target group which includes those logic circuit components which do not have an influence on the analysis point, and the graphic screen displays the logic circuit components separately in the target group and the non-target group. The apparatus is applied to design a logic circuit of an LSI, a PCB or the like.

Abstract: A CAD apparatus for designing wires for an LSI or a printed circuit board is improved in that it can detect and determine a wire which is very probably influenced by crosstalk noise accurately in a short time and allows to make it clear how to modify wires. The CAD apparatus comprises a CAD execution section for designing wires, a display section for displaying a wire condition designed by the CAD execution section, and a display control section for controlling the displaying condition of the display section. The display control section controls the display section to display wire patterns of wires on the LSI or the printed circuit board obtained by designing of wires by the CAD execution section as well as the signal propagation directions of the individual wires.

Abstract: A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (405) between arrival and required times for each node. If the actual arrival time for a particular node is after the time required to meet a predetermined design constraint of the node (407), a determination (411) is made regarding the effect of that element on the nodal slack for an incremental increase in the size of that element. Thereafter an element is selected (413) for sizing increase (415) in accordance with a weighting function and the process is repeated until all of the nodes in the integrated circuit have positive slack times (407,409).

Abstract: A configuration emulation circuit generates configuration signals to emulate a programmable Logic Device (PLD) in a configuration timing relationship and a configuration protocol relationship between a programming circuit and the PLD. The circuit includes a first circuit to emulate the PLD in the configuration timing relationship. The circuit also includes a second circuit to emulate the PLD in the configuration protocol relationship. The second circuit is coupled to receive a configuration mode signal and is responsive to the configuration mode signal.

Abstract: The vehicle power train control method and apparatus according to the invention secures both operability and safety by controlling an actual acceleration/deceleration to a target acceleration/deceleration requested by a driver under safe traveling condition, and changing the target acceleration/deceleration so as to take precedence for safe traveling if the driver encounters a dangerous traveling condition. According to the invention, acceleration/deceleration and speed of a motor vehicle are detected; a target acceleration/deceleration is determined; and a road condition such as a road gradient or presence or absence of a forward motor vehicle is detected to decide whether the road condition is dangerous. The target acceleration is changed if the condition is decided to be dangerous.