Abstract: A host data processing system which includes a plurality of input/output devices operates under the control of an enhanced version of the UNIX operating system. The host system includes an emulator which runs as an application process for executing user emulated system (ES) application programs. The emulator includes a number of emulated system executive service components operating in shared memory and an interpreter, an emulator monitor call unit (EMCU) and a number of server facilities operating in the host memory. The ES executive service command handler component is extended to accommodate a number of dual decor commands which invoke host system facilities to execute terminal based commands either synchronously or asynchronously through the automatic creation of host shell mechanisms directly accessible by emulated system users. The server facilities include a network terminal driver (NTD) server for executing emulated system user terminal requests through host system drivers.

Abstract: An efficient method for modifying a chip or package design allows for the creation of small shapes without excessive expansion of design data. A computer program takes a physical design, represented in a computer data file, and generates a modified version of the design in which fill holes have been added. Subsequently, when the modified design is processed, the resulting semiconductor chip or package will contain physical images of the added fill holes, with the effect of making local pattern density more uniform and hence reducing process-induced variations in feature size and shape.

Abstract: A method forms an analyzing model for use in finite element method analysis.

Abstract: Asynchronous combinatorial logic apparatus and method are provided that propagate data through a logic array at the speed of a raw combinational logic array and generate a functional output signal. The apparatus and method provide a minimum expected value of data propagation delay. In one embodiment, a particular data path is identified that has higher than average usage probability based on knowledge of the probabalistic distribution of data values, and the particular data path connecting devices located in the identified higher usage path are modified, such as by shortening the path, so that the path that is known to have a higher usage is made faster.

Abstract: In bending angle detection, a linear projected light image formed on the surface of a workpiece is photographed by a photographing device; the actual inclination angle of a specimen is stored as data in correspondence with the inclination angle and position of the specimen in an image; and the bending angle of the workpiece is obtained by accessing the data, with the inclination angle and position of the linear projected light image in an image produced by photographing. In main straight line extraction, main pixels are obtained from the distribution of the brightness of pixels aligned on specified axes and a main straight line is obtained from a plurality of main pixels. For extracting only a necessary straight line from an image including unnecessary straight lines, the photographing device is so disposed as to photograph a lower bender and a second straight line from the bottom end of the image is extracted.

Abstract: A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.

Abstract: A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.

Abstract: An automatic layout of a data-path circuit, whose performance and area are optimized, requires to input a data-path circuit, produce an external terminal directive branch having a start point placed on an input terminal group of the data-path circuit and an end point placed on an output terminal group of the same, and produce in-circuit directive branches corresponding to respective connecting lines between two circuit elements in the data-path circuit, each in-circuit directive branch having a start point placed on one circuit element supplying a signal to a related connecting line and an end point placed on the other circuit element receiving the signal from the same connecting line. Subsequently, a group circuit is produced based on the relationship between the in-circuit directive branches and the circuit elements, the group circuit comprising a plurality of circuit elements performing a series of logic processing per 1-bit signal.

Abstract: A computer-based method and program for improving a design of a circuit through analysis of a computer stored model of the circuit. Individual synchronization points are identified in the circuit at each of which a signal may be blocked or allowed to pass in response to appearance of a second signal at the synchronization point. The timing of the circuit is verified based on the individual synchronization points.

Abstract: A method of interactive feedback in semiconductor processing is provided which compensates for lithographic proximity effects, reactive ion etch loading effects, electromigration and stress due to layering.

Abstract: A method and apparatus for verifying an integrated circuit design composed of both synchronous and asynchronous regions. The computer implemented system imports a design combining synchronous and asynchronous regions and utilizes a static timing analyzer to automatically determine the boundaries of the asynchronous regions including input and output probe points at the inputs and outputs of the asynchronous regions. The static timing analyzer also generates a netlist of the asynchronous regions as well as certain information indicative of the signal arrival times of data sensed over the input probe points of the asynchronous regions. A functional simulator then uses test vectors generated for the primary inputs of the integrated circuit design and automatically determines a set of test vectors specifically for the asynchronous portion by monitoring the input probe points. This can be done for each asynchronous region.

Abstract: A method is disclosed to execute an event driven logic simulation to check the function of a logic circuit, by using a logic simulator. The logic simulator includes at least one data base and a processing unit having a dummy element synthesizer. The dummy element is a tool for detecting changes in signals at a target cell or a target terminal. At the time that the logic simulation starts, the dummy element synthesizer produces the dummy element defining data, referring to or based on information stored in the data base, and combines the dummy element defining data and the logic circuit design data. Thus, for example, timing simulation at a target cell in the logic circuit or the check of the number of times of changes in signals at a target output terminal of the logic circuit, is executed during the event driven logic simulation.

Abstract: A method and apparatus for deriving total lateral diffusion in MOS transistors includes deriving (40) a DC model. The DC model is then verified (42) with a multifinger transistor. The gate of the multifinger transistor is then isolated (44). Voltage pulses are then applied (46) to the multifinger transistor, and the current attributable to the voltage pulses is measured (48). Using the model, estimates of the total lateral diffusion are adjusted (50) until the modelled current matches the measured current. Finally, the complete and accurate AC/DC model can be used (52) by circuit designers to design various circuits that will operate as designed when implemented.

Abstract: A universal sequential logic circuit is constructed from a rectilinear array of elementary logic "cells", with a relatively large number of logic states embodied in a relatively small array. The set of states from a state-machine description of the logic function desired to be performed is compiled into a software association of cellular array states with each state-machine state (4), and the set of transitions from the state-machine description is compiled into a software association of logical connections between cells. The cellular array performs the state-machine function under software control. The rectilinear array (1a) generally embodies one bit of cellular array state information for each row of logic cells, stored in diagonal cells of the array called "memory cells" (2). Non-diagonal cells of the array called "function cells" (3) are controlled by stored software, which controls the transfer of cellular array state information from each row to each other.

Abstract: Correction coefficients which permit effective linearization of an electronic scale over a measurement range may be determined by loading the scale individually and in combination with loads, at least one of the loads being unknown and uncalibrated.

Abstract: A method and on-chip architecture are disclosed for multiplexing signals from selected external interconnect buses to chip internal buses such that bus rerouting can be implemented programmably without substantially affecting timing relations between time-parallel signals of a rerouted bus. An on-chip switch matrix is provided having N input lines crossing with M output lines to provide N times M crosspoints. A plurality of substantially less than N times M programmable interconnect switches (PIP's) are distributed symmetrically among the N.multidot.M crosspoints such that a same first number of interconnect switches (PIP's) are found along each of the N input lines thereby providing equal loading on each input line. The plurality of programmable interconnect switches (PIP's) are further distributed among the N.multidot.M crosspoints such that a same second number of interconnect switches (PIP's) are found along each of the M output lines thereby providing equal loading on each output line.

Abstract: A vibration/noise control system controls vibrations and noises generated with a periodicity or a quasi-periodicity from a vibration/noise source having at least a rotating member. A self-expanding engine mount is arranged in at least one of vibration/noise transmission paths and is driven by a driving signal generated by the system. A vibration error sensor detects an error signal exhibiting a difference between the driving signal and the vibrations and noises. A reference sine wave is generated, which is superposed on a control signal for controlling the vibration/noise source, to thereby drive the self-expanding engine mount. A transfer characteristic of a portion of at least one of the vibration/noise transmission paths is identified based on the reference sine wave, a delayed sine wave delayed by a predetermined delay period M relative to the reference sine wave, and the error signal.

Abstract: Packaged signal routing circuits (e.g. on printed circuit cards or boards), route pulse signals with very short rise times from a lossy driver to multiple devices. In these routing circuits, a complex network of conductors branches from a common junction adjacent the driver output into multiple (in the disclosed embodiment, three) conduction paths of unequal length. In accordance with the invention, the internal impedance of the driver is matched to the aggregate charateristic impedance of the branch paths, and a lossless compensating circuit is attached to a shortest branch path. The compensating circuit is designed to transfer signal reflections of predetermined form to the branching junction at the driver via the shortest branch. Without the compensating circuit, reflections presented to the branching junction from the shortest branch are dissimilar to reflections presented to that junction from other branch paths.

Abstract: Apparatus for determining the present location of, or time of observation by, an observer in the vicinity of the Earth's surface. The apparatus provides a Satellite Positioning System (SATPS), such as GPS or GLONASS, in a portable device or card that is built to the I.E.E.E. PC/104 Standard, which is a variation of the I.E.E.E. P996 Standard for personal computer buses. The PC/104/SATPS Card includes an SATPS antenna to receive (and frequency downconvert, if necessary) SATPS signals from one or more SATPS satellites, a microprocessor programmed to receive the SATPS signals from the antenna and to perform calculations to determine the spatial location of the antenna and/or the time of observation by the antenna. The PC/104/SATPS Card has a buffer and a format translator to compensate for SATPS signal latency and for differences in SATPS signal arrival rate and PC/104 signal processing rate and/or to translate signals from SATPS format to whatever format the microprocessor uses.

Abstract: A technique for extracting a gate level logic model from transistor networks has been described. The resultant logic model can be technology dependent or technology independent, depending on control parameters and environment of the program. It handles all CMOS logic families including static, precharge, pass CMOS switching network and self-resetting families. The output gate level model can be used in variety of applications including but not limited to logic simulation, verification, test generation, debug, diagnosis, etc.