Abstract: An apparatus for forming input data for a logic simulator executes the operation processing so as to convert a net list using elements as bases into a net list using cell units as bases, and feeds the net list to a logic simulator. The apparatus for forming input data for a logic simulator is constituted by a processing device which, for a net list which uses elements as units and is constituted by connection data among the elements including parasitic resistances and parasitic capacitances, feeds, to a logic simulator, the data related to nets, parasitic resistances and parasitic capacitances but excluding those nets, and parasitic resistances and parasitic capacitances that are completed in a cell.

Abstract: In order to effectively explore a binary decision diagram for synthesizing a logic circuit, a tentative circuit comprised of AND gates and OR gates is synthesized from a logic function. The number of gates in this circuit to which two input variables are simultaneously associated are counted and used as correlation between the two input variables. A correlation matrix for correlation among all of the input variables is generated. The input variables are sequentially grouped from a set of input variables with strongest correlation in the correlation matrix: These groups are registered into a correlation tree, and an intergroup correlation tree is produced. These groups are sequentially selected from a group with the least correlation, and the intragroup order of the selected group is changed from one to another. A binary decision diagram is explored which satisfies the most appropriate condition in that group (such as the minimum number of nodes, the minimum delay, and the minimum area).

Abstract: A reduced power programmable logic array is disclosed. The circuit includes an AND array, coupled through product term lines to an output OR array. Pull-up devices in the OR array are gated to one of the active product term lines. Also disclosed is method for choosing a product term line for gating pull-up devices such that power consumption in the pull-up devices is minimized.

Abstract: An improved frequency counter for more reliably reading the frequency of low level signals by employing a method of separating the desired signal from undesirable noise related signals, wherein the frequency counter comprises signal input amplifier circuitry, a frequency modulator circuit for phase shifting the self-oscillation frequency of the undesired signal to isolate it from the valid signal, a prescaler circuit, a frequency or pulse counter driven by the output of the prescaler, and a correlator circuit for differentiating the self-oscillation frequencies from the main signal frequency so as to reduce false correlations between the self-oscillation, or noise, and valid signals.

Abstract: A high-level synthesis apparatus synthesizes a large-scale logic circuit. The apparatus has a unit for generating a control description graph according to a behavioral description graph written in a behavioral description language; a unit for sorting the control description graph according to control conditions and extracting single flows including partial graphs or closed loops from the sorted control description graph; a unit for providing an initial circuit; a unit for dividing the single flows into execution steps; a unit for allocating hardware parts of the initial circuit to the execution steps; and a unit for converting each of the single flows into a finite state machine and combining the finite state machines into one. This apparatus optimizes each single flow and adds parts to or modifies the initial circuit, to synthesize a large-scale circuit.

Abstract: A software configuration management and test System for tracking and testing an ASIC design software package includes a library of test programs, an autodetector, an autoverifier, a failure report generator, and a package information logger. The System automatically selects which tests to run on the tools package depending on which portions of which tools have been updated, and then automatically sequences the tools package through the selected tests. By automating the testing process, the System achieves automation, standardization, completeness, and a systematic approach to testing. By greatly reducing test turnaround time, the System also facilitates concurrent engineering.

Abstract: A computer implemented process and system for providing a test ready (TR) compiler with specific information regarding the impact of added scannable cells and resources on its mission mode design. In so doing, the TR compiler optimizes more effectively for added test resources (e.g., scannable cells and other scan routing resources) so that predetermined performance and design related constraints of the mission mode design are maintained. The TR compiler translates generic sequential cells into technology dependent non-scan cells. In the TR compiler, during replacement, scannable memory cells are used in place of these non-scan memory cells specified within the mission mode circuitry. In this way, the TR compiler is informed of the characteristics of the scannable memory cells during optimization. For test, the scannable memory cells are chained to each other to form chain chains of sequential cells.

Abstract: The present invention provides a suspension control apparatus for a vehicle ensuring good comfort regardless of a waving road surface condition. A control signal adjusting portion sends a control signal for decreasing a damping coefficient for an extension side to a control signal emitting portion when an absolute value of downward acceleration of sprung mass exceeds a sprung mass acceleration reference value. When the vehicle reaches the top of an undulation and the absolute value of the downward acceleration of the sprung mass exceeds the sprung mass acceleration reference value, the control signal adjusting portion sends the control signal for decreasing a damping coefficient for the extension side to the control signal emitting portion so that a shock absorber of variable damping coefficient type can easily be displaced toward the extension side.

Abstract: A logic emulation system that verifies a target logic circuit and evaluates its performance efficiently divides the design data of a target logic circuit into a plurality of small-scale logic circuits and a connection circuit for interconnecting the small-scale logic circuits, thereby creating an equivalent circuit of the target logic circuit. The logic emulation system judges, when a logical design change to the target logic circuit prompts the comparison of the data of the equivalent circuit of the logic circuit before the logical change with the data after the logical change, whether it is feasible to implement the design data on the logically changed logic circuit by adding one or more small-scale logic circuits, and by altering the connection circuit accordingly.

Abstract: A plurality of cells which have input terminals and output terminals on four sides are divided into a plurality of groups of cells. The plurality of cells are placed in an array form at positions which are either adjacent or nonadjacent. A plurality of groups of cells are placed one after another such that the resulting layout becomes substantially rectangular or square. Power buses are routed parallel to each other, and power supply lines are routed from the power buses to cells. Data lines are routed between the terminals of the cells.

Abstract: A method of electrically modeling a semiconductor package is provided. The method reduces computation time for mutual inductance calculations between interconnect lines of the semiconductor package. Only interconnect within a predetermined distance of an interconnect line being modeled is calculated for mutual inductance. The predetermined distance is selected such that any interconnect line greater than the predetermined distance away from the interconnect line being modeled produces a negligible or small mutual inductance. This greatly reduces the number of calculations for semiconductor packages having a large number of interconnect lines. Each interconnect line modeled is broken into segments for calculating mutual inductance. An algorithm is used that calculates the mutual inductance between a pair of arbitrarily oriented straight line metal segments.

Abstract: A system and method for entering a circuit design into a computer using a schematic capture package. The schematic capture package is modified to include a library of state flow components represented by symbols which can be connected to produce a desired representation of the circuit design. The system allows a circuit design to be displayed on a video terminal using both state flow diagram and the schematic diagram symbols, with terminals of the state flow symbols connecting to terminals of the schematic symbols. The state flow diagram using state flow symbols is combined with a schematic diagram including schematic symbols to generate a netlist representing the combined circuit.

Abstract: A computer-aided design method and apparatus for compacting semiconductor circuit layouts to meet a specified set of design rules begins by fracturing a specified circuit layout into a set of trapezoids and storing the resulting cells in a database identifying the boundaries of each cell, and the cell adjacent each boundary. The method additionally includes a procedure for minimizing wire lengths in the compacted layout. Nonempty cells are identified as being of specific materials, and empty spaces between cells are represented. For each cell boundary, the database also stores data representing the boundary edge's end points. Neighboring cells on the same and related layers of the circuit layout share edges in the database. When a point on an edge of a cell is moved, the edge of each neighboring cell that shares that point is also moved. To adjust a circuit layout, the cells in the layout are processed in a sorted order.

Abstract: A design verification apparatus for verifying the suitability of a design to the objectives of a design for an industrial product is disclosed. New design data specification is input. Old design data closest to the new design data is fetched from a design example database and is revised according to the new design specifications. Specification items and tolerance ranges for the specification items are generated based on the input specifications. Verification items based on the old design data and tolerance ranges for the verification items are fetched from a knowledge database. Verify values for the specification items and for the verification items are calculated. The verify values obtained according to the specification items are compared with the tolerance ranges for the specification items, and the verify values obtained according to the verification items are compared with the tolerance ranges for the verification items.

Abstract: An electronic system for use with a host computer. The system includes electronic circuitry including a first semiconductor chip generally operable for a first function and also adapted for input and output of emulation signals. This is combined with emulation circuitry including a second semiconductor chip adapted for connection to the host computer. The emulation circuitry is connected to the electronic circuitry to generate emulation signals to input to the electronic circuitry and to accept emulation signals from the electronic circuitry. A physical assembly supports the emulation circuitry and the electronic circuitry as a unit. Other electronic systems and emulation and testing devices, cables, systems and methods are also disclosed.

Abstract: Measurement of the test coverage of digital simulation of electronic circuitry is obtained (54). A Composite Circuit Model (60) has two parts: a Target Circuit Model (64) and an Environment Circuit Model (62). The Environment Circuit Model (62) models the behavior of inputs to the Target Circuit (64). The Composite Circuit Model (60) is translated into implicit FSM representations utilizing BDDs. A State Bin Transition Relation is formed which represents allowable transitions among user-specified sets of states or State Bins, and a representation of the reachable State Bins is built (94). A comparison is made (102) between data accumulated over one or more simulations (40) of the Target Circuit (64) and the data contained in the State Bin Transition Relation and the representation of the reachable State Bins.

Abstract: A control target surveillance system capable of acquiring positional data of a control target in a control zone at high precision with fewer communications lines in a short period of time. A D. GPS ground station obtains differential data with respect to positional data based on a GPS signal from a GPS satellite, and sends this data to a control target to compensate the positional data obtained from the GPS signal. A surveillance cycle is time-divided by the number of SSR codes, individual time slots are associated with the SSR codes, and each control target is allowed.

Abstract: The temperature of the circuit to be verified is evaluated. A simulation executing section (101) executes logic simulation of the circuit to be verified expressed in function block units at function block level. A circuit action extracting section (103) extracts an actin mode of a function block in its process. A total current consumption calculating section (105) calculates the total current consumption which is the current consumed in the entire circuit to be verified, on the basis of the data of current consumption in each action mode and extracted action mode. An average current calculating section (107) calculates the average current which is the average of the total current consumption over the check period, reflecting the thermal characteristic of the circuit to be verified. An allowable temperature judging section (109) calculates the temperature of the circuit to be verified according to this average current, and compares with an allowable current.

Abstract: Probe-point placement methods are described. A layout description, a netlist description and a cross-reference description of an IC are retrieved from storage. The data structures associate with each net name a list of polygons. Polygons of a selected net are broken into segments of a specified step size. Each segment is evaluated in accordance with a set of prober rules. Values produced by the prober rules are weighted and combined to obtain a prober score for each segment. The prober score indicates suitability of the corresponding net location for probing. If the best prober score indicates an optimal segment exists for probing, the coordinates of that segment are stored and used to direct a probe to the corresponding location of the IC. If the best prober score indicates no optimal segment exists for probing, each segment of the net is evaluated in accordance with a set of probe-point cutter rules.

Abstract: A method for designing a circuit layout which includes the steps of supplying a predictive capacitance value for at least one net of a circuit layout, and placing and routing all nets of the circuit layout using at least one predictive capacitance value as a layout design constraint.